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公开(公告)号：US20250113503A1
公开(公告)日：2025-04-03
申请号：US18478840
申请日：2023-09-29
Applicant: Intel Corporation
Inventor： Nicolas Butzen , Harish K. Krishnamurthy , Khondker Ahmed , Nachiket Desai , Su Hwan Kim , Krishnan Ravichandran , Kaladhar Radhakrishnan , Jonathan Douglas
IPC: H01L23/00 , H01L23/498 , H01L25/065
Abstract: Embodiments herein relate to techniques to integrate a capacitive voltage regulator in an integrated circuit (IC) package. The voltage regulator may provide a power supply to one or more load domains in the IC package. The transistors of the voltage regulator may be included on the same die as one or more of the load domains, another die, and/or an interposer of the IC package. The capacitors may be included in the same die as the transistors, in the interposer, in a package layer (e.g., package core), and/or in the same die as one or more of the load domains. Accordingly, the voltage regulator can be integrated close to the relevant load domains, delivering power with short current paths and thereby providing reduced input impedance, output impedance, and associated losses compared with prior techniques. Other embodiments may be described and claimed.
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公开(公告)号：US20250105144A1
公开(公告)日：2025-03-27
申请号：US18474160
申请日：2023-09-25
Applicant: Intel Corporation
Inventor： Su Hwan Kim , Harish K. Krishnamurthy , Nachiket Desai , Khondker Ahmed , Nicolas Butzen , Krishnan Ravichandran , Kaladhar Radhakrishnan
IPC: H01L23/522 , H01L23/498 , H01L25/065 , H02M3/335
Abstract: Embodiments herein relate to a voltage regular (VR) formed from die stacked on a package base layer. The die can include a load die stacked on a VR die, with an intermediate layer between the two dies. The VR can include an inductor or transformer as a charge transfer component formed between the dies. For example, the inductor or transformer windings can wind around the intermediate layer and include portions of top metal layers of the VR and load die, where the load die is inverted in the stack. The intermediate layer can be magnetic or non-magnetic for an inductor, or magnetic for a transformer. The VR can optionally be divided among two dies. The VR die may have a gallium nitride substrate to handle a higher input voltage, while the load die comprises a silicon substrate.
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公开(公告)号：US12261526B2
公开(公告)日：2025-03-25
申请号：US17323837
申请日：2021-05-18
Applicant: Intel Corporation
Inventor： Harish K. Krishnamurthy , Xun Sun , Krishnan Ravichandran
Abstract: A computational current sensor, that enhances traditional Kalman filter based current observer techniques, with transient tracking enhancements and an online parasitic parameter identification that enhances overall accuracy during steady state and transient events while guaranteeing convergence. During transient operation (e.g., a voltage droop), a main filter is bypassed with estimated values calculated from a charge balance principle to enhance accuracy while tracking transient current surges of the DC-DC converter. To address the issue of dependency on a precise model parameter information and further improve accuracy, an online identification algorithm is included to track the equivalent parasitic resistance at run-time.
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公开(公告)号：US20250096200A1
公开(公告)日：2025-03-20
申请号：US18469201
申请日：2023-09-18
Applicant: Intel Corporation
Inventor： Nicolas Butzen , Harish K. Krishnamurthy
IPC: H01L25/065 , H01L25/18 , H02M3/158
Abstract: Embodiments herein relate to a voltage regular (VR) formed by components which are distributed over a stack of dice or wafers. Separate VRs can be provided in separate dice or wafers, where their outputs are coupled at an output path. A common control circuit can be used to control each VR. Passive components of a VR can be distributed on separate dice. For example, capacitors or inductors on the different dice or wafers can be coupled in parallel or in series, respectively. The stack can include dice or wafers of different types, such as silicon and Gallium Nitride. A first VR on a first type of die or wafer can be arranged in cascade with a second VR on a second type of die or wafer. The components in the different dice or wafers can be coupled by vias such as through-silicon vias.
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公开(公告)号：US20170025953A1
公开(公告)日：2017-01-26
申请号：US15188205
申请日：2016-06-21
Applicant: Intel Corporation
Inventor： Nicholas P. COWLEY , Harish K. Krishnamurthy , Ruchir Saraswat
IPC: H02M3/158 , H01L25/065 , H02M1/088 , H02M3/157
CPC classification number: H02M3/158 , H01L25/0657 , H01L2225/06541 , H02M1/088 , H02M3/157 , H02M2001/008
Abstract: Described is an apparatus which comprises: a first bridge to be coupled to a first load; a first Pulse Width Modulation (PWM) circuit to drive the first bridge; a second bridge to be coupled to a second load; and a second PWM circuit to drive the second bridge, wherein the first PWM circuit is controlled by a first digital word separate from a second digital word, wherein the second PWM circuit is controlled by the second digital, and wherein the second digital word is derived from the first digital word.
Abstract translation: 描述了一种装置，其包括：要耦合到第一负载的第一桥; 用于驱动第一桥的第一脉宽调制（PWM）电路; 耦合到第二负载的第二桥; 以及驱动所述第二桥的第二PWM电路，其中所述第一PWM电路由与第二数字字分离的第一数字字来控制，其中所述第二PWM电路由所述第二数字控制，并且其中所述第二数字字被导出 从第一个数字字。
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Patent Agency Ranking
6.发明公开公开(公告)号：US20230341444A1
公开(公告)日：2023-10-26
申请号：US17727153
申请日：2022-04-22
Applicant: Intel Corporation
Inventor： Nachiket Desai , Harish K. Krishnamurthy
CPC classification number: G01R19/2513 , H01L29/783
Abstract: Embodiments herein relate to a current sensor for a power converter such as a buck converter. The power converter is fabricated on a high bandgap semiconductor die while the current sensor includes a portion on the same die and a portion on a silicon die. The portion on the same die includes a sense transistor, while the portion on the silicon die includes a feedback circuit for controlling a voltage of the sense transistor to ensure it is biased according to the bias of a switching transistor of the power converter. A current of the sense transistor can then be processed such as by an averaging or sampling process.
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公开(公告)号：US10345881B2
公开(公告)日：2019-07-09
申请号：US15653764
申请日：2017-07-19
Applicant: Intel Corporation
Inventor： Ramnarayanan Muthukaruppan , Harish K. Krishnamurthy , Mohit Verma , Pradipta Patra , Uday Bhaskar Kadali
IPC: G06F9/00 , G06F1/32 , G06F1/3234 , G06F1/3296 , G06F1/324
Abstract: Described is an apparatus comprising: first and second processing cores; and a PCU which is operable to: generate a first VID for an off-die regulator external to the apparatus, the first VID resulting in a first power supply for the first processing core; and generate a second VID different from the first VID, the second VID resulting in a second power supply for the second processing core. Described is an apparatus comprising: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a processing core, and to receive a second power supply as input; an ADC to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative and to generate the digital bus for controlling the plurality of power-gate transistors.
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公开(公告)号：US09948186B2
公开(公告)日：2018-04-17
申请号：US15188205
申请日：2016-06-21
Applicant: Intel Corporation
Inventor： Nicholas P. Cowley , Harish K. Krishnamurthy , Ruchir Saraswat
CPC classification number: H02M3/158 , H01L25/0657 , H01L2225/06541 , H02M1/088 , H02M3/157 , H02M2001/008
Abstract: Described is an apparatus which comprises: a first bridge to be coupled to a first load; a first Pulse Width Modulation (PWM) circuit to drive the first bridge; a second bridge to be coupled to a second load; and a second PWM circuit to drive the second bridge, wherein the first PWM circuit is controlled by a first digital word separate from a second digital word, wherein the second PWM circuit is controlled by the second digital, and wherein the second digital word is derived from the first digital word.
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公开(公告)号：US20250103074A1
公开(公告)日：2025-03-27
申请号：US18474147
申请日：2023-09-25
Applicant: Intel Corporation
Inventor： Harish K. Krishnamurthy , Nicolas Butzen , Khondker Ahmed , Nachiket Desai , Su Hwan Kim , Krishnan Ravichandran , Kaladhar Radhakrishnan , Jonathan Douglas
IPC: G05F1/56
Abstract: Embodiments herein relate to a voltage regular (VR) formed from dies stacked on a package base layer. The VR can include a first part on a first die and a second part on a second die, where the different parts are selected based on characteristics of the respective die such as their voltage domains or technologies. In a capacitor-based VR, an input capacitor and switches subject to a relatively high input voltage can be provided in the first die, while a flying capacitor, output capacitor and switches subject to a relatively low output voltage can be provided in the second die. In an inductor-based VR, an inductor and one or more switches subject to a relatively high input voltage can be provided in the first die, while an output capacitor subject to a relatively low output voltage can be provided in the second die.
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公开(公告)号：US20240386937A1
公开(公告)日：2024-11-21
申请号：US18318659
申请日：2023-05-16
Applicant: Intel Corporation
Inventor： Su Hwan Kim , Chi-Hsiang Huang , Harish K. Krishnamurthy
IPC: G11C11/4074 , H02M1/00 , H02M3/07 , H02M3/158
Abstract: Various embodiments herein provide a switched capacitor voltage converter with a subset of one or more phases that selectively provide a decoupling capacitance. The voltage converter may include multiple phases coupled in parallel between an input terminal and an output terminal. The individual phases may include a capacitor and a set of switches. A first subset of one or more of the phases may operate in a switching mode in which the respective set of switches open and close to generate an output voltage at the output terminal based on an input voltage at the input terminal. The voltage converter may further include a second subset of one or more phases that are selectively operable in the switching mode or in a decoupling mode. In the decoupling mode, the switches of the respective phase may maintain the capacitor coupled between the output terminal and ground. Other embodiments may be described and claimed.
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