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公开(公告)号：US20250103074A1
公开(公告)日：2025-03-27
申请号：US18474147
申请日：2023-09-25
Applicant: Intel Corporation
Inventor： Harish K. Krishnamurthy , Nicolas Butzen , Khondker Ahmed , Nachiket Desai , Su Hwan Kim , Krishnan Ravichandran , Kaladhar Radhakrishnan , Jonathan Douglas
IPC: G05F1/56
Abstract: Embodiments herein relate to a voltage regular (VR) formed from dies stacked on a package base layer. The VR can include a first part on a first die and a second part on a second die, where the different parts are selected based on characteristics of the respective die such as their voltage domains or technologies. In a capacitor-based VR, an input capacitor and switches subject to a relatively high input voltage can be provided in the first die, while a flying capacitor, output capacitor and switches subject to a relatively low output voltage can be provided in the second die. In an inductor-based VR, an inductor and one or more switches subject to a relatively high input voltage can be provided in the first die, while an output capacitor subject to a relatively low output voltage can be provided in the second die.
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2.发明授权公开(公告)号：US11537375B2
公开(公告)日：2022-12-27
申请号：US16550134
申请日：2019-08-23
Applicant: Intel Corporation
Inventor： Julien Sebot , Edward A. Burton , Nasser A. Kurd , Jonathan Douglas
Abstract: An apparatus and method is described that digitally coordinates dynamically adaptable clock and voltage supply to significantly reduce the energy consumed by a processor without impacting its performance or latency. A signal is generated that indicates a long latency operation. This signal is used to reduce power supply voltage and frequency of the adaptable clock. An early resume indicator is generated a few nanoseconds before normal operations are about to resume. This early resume signal is used to power up the power-downed voltage regulator, and/or can increase frequency and/or supply voltage back to normal level before normal processor operations are about to resume.
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3.发明申请公开(公告)号：US20210055921A1
公开(公告)日：2021-02-25
申请号：US16550134
申请日：2019-08-23
Applicant: Intel Corporation
Inventor： Julien Sebot , Edward A. Burton , Nasser A. Kurd , Jonathan Douglas
Abstract: An apparatus and method is described that digitally coordinates dynamically adaptable clock and voltage supply to significantly reduce the energy consumed by a processor without impacting its performance or latency. A signal is generated that indicates a long latency operation. This signal is used to reduce power supply voltage and frequency of the adaptable clock. An early resume indicator is generated a few nanoseconds before normal operations are about to resume. This early resume signal is used to power up the power-downed voltage regulator, and/or can increase frequency and/or supply voltage back to normal level before normal processor operations are about to resume.
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Patent Agency Ranking
公开(公告)号：US20250113503A1
公开(公告)日：2025-04-03
申请号：US18478840
申请日：2023-09-29
Applicant: Intel Corporation
Inventor： Nicolas Butzen , Harish K. Krishnamurthy , Khondker Ahmed , Nachiket Desai , Su Hwan Kim , Krishnan Ravichandran , Kaladhar Radhakrishnan , Jonathan Douglas
IPC: H01L23/00 , H01L23/498 , H01L25/065
Abstract: Embodiments herein relate to techniques to integrate a capacitive voltage regulator in an integrated circuit (IC) package. The voltage regulator may provide a power supply to one or more load domains in the IC package. The transistors of the voltage regulator may be included on the same die as one or more of the load domains, another die, and/or an interposer of the IC package. The capacitors may be included in the same die as the transistors, in the interposer, in a package layer (e.g., package core), and/or in the same die as one or more of the load domains. Accordingly, the voltage regulator can be integrated close to the relevant load domains, delivering power with short current paths and thereby providing reduced input impedance, output impedance, and associated losses compared with prior techniques. Other embodiments may be described and claimed.
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公开(公告)号：US20220413536A1
公开(公告)日：2022-12-29
申请号：US17359413
申请日：2021-06-25
Applicant: Intel Corporation
Inventor： Amit K. Jain , Mauricio Aguilar Salas , Jonathan Douglas , Anant Deval
IPC: G05F1/59 , G06F1/3203 , G05F1/575
Abstract: Techniques and mechanisms for determining an operational mode of a voltage regulator. In an embodiment, an integrated circuit (IC) die is coupled to receive power from a voltage regulator (VR) via a power delivery network (PDN) which comprises circuitry in or on a substrate, such as that of a printed circuit board. The IC die receives from the substrate information indicating a characteristic of a parasitic impedance at the substrate. Based on the information, a controller unit at the IC die selects one of multiple VR modes which each correspond to a respective one of different parasitic impedance characteristics. The controller then signals the VR to provide the selected mode. In an embodiment one of the VR modes corresponds to a relatively high impedance, and also corresponds to a relatively stable sensitivity function in a frequency range above a control bandwidth.
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6.发明申请公开(公告)号：US20250103075A1
公开(公告)日：2025-03-27
申请号：US18474156
申请日：2023-09-25
Applicant: Intel Corporation
Inventor： Khondker Ahmed , Nicolas Butzen , Nachiket Desai , Su Hwan Kim , Harish K. Krishnamurthy , Krishnan Ravichandran , Kaladhar Radhakrishnan , Jonathan Douglas
IPC: G05F1/56
Abstract: Embodiments herein relate to a stacked semiconductor structure which includes a first voltage regulator (VR), external to a package, for supplying current to a compute die in the package. When the required current exceeds a threshold, an additional current source is activated. The additional current source can include a second VR, also external to the package, for supplying current to an integrated voltage regulator (IVR) in the package. The IVR performs voltage down conversion and current multiplication to output a portion of the required current above the threshold, while the output of the first VR is capped at the threshold.
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公开(公告)号：US12164322B2
公开(公告)日：2024-12-10
申请号：US17359413
申请日：2021-06-25
Applicant: Intel Corporation
Inventor： Amit K. Jain , Mauricio Aguilar Salas , Jonathan Douglas , Anant Deval
IPC: G05F1/59 , G05F1/575 , G06F1/3203
Abstract: Techniques and mechanisms for determining an operational mode of a voltage regulator. In an embodiment, an integrated circuit (IC) die is coupled to receive power from a voltage regulator (VR) via a power delivery network (PDN) which comprises circuitry in or on a substrate, such as that of a printed circuit board. The IC die receives from the substrate information indicating a characteristic of a parasitic impedance at the substrate. Based on the information, a controller unit at the IC die selects one of multiple VR modes which each correspond to a respective one of different parasitic impedance characteristics. The controller then signals the VR to provide the selected mode. In an embodiment one of the VR modes corresponds to a relatively high impedance, and also corresponds to a relatively stable sensitivity function in a frequency range above a control bandwidth.
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公开(公告)号：US11271475B2
公开(公告)日：2022-03-08
申请号：US16440901
申请日：2019-06-13
Applicant: Intel Corporation
Inventor： Rinkle Jain , Jonathan Douglas , Shivadarshan Rajeurs
Abstract: Disclosed is an N:1 (where N is an integer such as 3 or higher) resonant star topology converter to generate an input supply (e.g., 1.8V) for a processor (e.g., a system-on-chip (SOC)) from a higher power supply source (e.g., 12.6V) such as a battery or other source. The resonant star topology based regulator can be realized by a combination of on-die and on-package components as opposed to voltage regulators on motherboard with discrete inductor and capacitors. In one example, capacitors of the N:1 resonant star topology are implemented as multilayer ceramic capacitors (MLCC). The architecture of the N:1 resonant star topology based regulator results in high bandwidth. For example, compared to traditional step-down voltage regulators, the N:1 resonant star topology based regulator exhibits ten times higher bandwidth.
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