公开(公告)号：US20240143505A1

公开(公告)日：2024-05-02

申请号：US18393793

申请日：2023-12-22

Applicant: Intel Corporation

Inventor： Amruta MISRA ,  Ajay RAMJI ,  Rajendrakumar CHINNAIYAN ,  Chris MACNAMARA ,  Karan PUTTANNAIAH ,  Pushpendra KUMAR ,  Vrinda KHIRWADKAR ,  Sanjeevkumar Shankrappa ROKHADE ,  John J. BROWNE ,  Francesc GUIM BERNAT ,  Karthik KUMAR ,  Farheena Tazeen SYEDA

IPC: G06F12/0811

CPC classification number: G06F12/0811

Abstract: Methods and apparatus for dynamic selection of super queue size for CPUs with higher number of cores. An apparatus includes a plurality of compute modules, each module including a plurality of processor cores with integrated first level (L1) caches and a shared second level (L2) cache, a plurality of Last Level Caches (LLCs) or LLC blocks and a plurality of memory interface blocks interconnect via a mesh interconnect. A compute module is configured to arbitrate access to the shared L2 cache and enqueue L2 cache misses in a super queue (XQ). The compute module further is configured to dynamically adjust the size of the XQ during runtime operations. The compute module tracks parameters comprising an L2 miss rate or count and LLC hit latency and adjusts the XQ size as a function of these parameters. A lookup table using the L2 miss rate/count and LLC hit latency may be implemented to dynamically select the XQ size.

公开(公告)号：US20230153121A1

公开(公告)日：2023-05-18

申请号：US18095998

申请日：2023-01-11

Applicant: Intel Corporation

Inventor： Yuzhang LUO ,  Haoxiang SUN ,  Siming WAN ,  Laurent COQUEREL ,  John J. BROWNE ,  Chris MACNAMARA ,  Fei Z. WANG

IPC: G06F9/445 ,  G06F11/34

CPC classification number: G06F9/44505 ,  G06F11/3409

Abstract: A machine-readable storage medium having program code that when processed by one or more processing cores causes a method to be performed. The method includes determining from program code that is scheduled for execution and/or is being scheduled for execution that an accelerator is expected to be invoked by the program code. The program code to implement one or more application software processes. The method also includes, in response to the determining, causing the accelerator to wake up from a sleep state before the accelerator is first invoked from the program code's execution.

公开(公告)号：US20190199646A1

公开(公告)日：2019-06-27

申请号：US16287339

申请日：2019-02-27

Applicant: Intel Corporation

Inventor： Jasvinder SINGH ,  John J. BROWNE ,  Tomasz KANTECKI ,  Chris MACNAMARA

IPC: H04L12/869 ,  H04L12/873 ,  H04L12/863 ,  H04L12/877 ,  H04L12/861 ,  H04L12/927 ,  H04L12/911

CPC classification number: H04L47/58 ,  H04L47/522 ,  H04L47/525 ,  H04L47/60 ,  H04L47/6215 ,  H04L47/74 ,  H04L47/805 ,  H04L47/808 ,  H04L49/9031

Abstract: Packets are differentiated based on their traffic class. A traffic class is allocated bandwidth for transmission. One or more core or thread can be allocated to process packets of a traffic class for transmission based on allocated bandwidth for that traffic class. If multiple traffic classes are allocated bandwidth, and a traffic class underutilizes allocated bandwidth or a traffic class is allocated insufficient bandwidth, then allocated bandwidth can be adjusted for a future transmission time slot. For example, a higher priority traffic class with excess bandwidth can share the excess bandwidth with a next highest priority traffic class for use to allocate packets for transmission for the same time slot. In the same or another example, bandwidth allocated to a traffic class depends on an extent of insufficient allocation or underutilization of allocated bandwidth such that a traffic class with insufficient allocated bandwidth in one or more prior time slot can be provided more bandwidth in a current time slot and a traffic class with underutilization of allocated bandwidth can be provided with less allocated bandwidth for a current time slot.

公开(公告)号：US20230342458A1

公开(公告)日：2023-10-26

申请号：US18214870

申请日：2023-06-27

Applicant: Intel Corporation

Inventor： Marcel CORNU ,  Tomasz KANTECKI ,  John J. BROWNE

IPC: G06F21/55 ,  G06F12/084

CPC classification number: G06F21/556 ,  G06F12/084 ,  G06F2212/1052

Abstract: Examples include techniques to mitigate or prevent cache-based side-channel attacks to a cache. Examples include use of assigned class of service (COS) assigned to cores of a process to determine whether to notify an OS of a potential malicious application attempting to access a cache line cached to a processor cache. Examples also include marking pages in an application memory address space of a processor cache as unflushable to prevent a potentially malicious application from accessing sensitive data loaded to the application memory address space of the processor cache.

公开(公告)号：US20230289197A1

公开(公告)日：2023-09-14

申请号：US18130415

申请日：2023-04-03

Applicant: Intel Corporation

Inventor： Gordon MCFADDEN ,  Laurent COQUEREL ,  Fei Z. WANG ,  John J. BROWNE

IPC: G06F9/445 ,  G06F12/02

CPC classification number: G06F9/44505 ,  G06F12/0292 ,  G06F2212/7201

Abstract: A method is described. The method includes repeatedly reading accelerator telemetry data from register and/or memory space allocated for the keeping of the accelerator telemetry data and writing the accelerator telemetry data into a physical file structure within memory and/or mass storage. The method also includes repeatedly reading the accelerator telemetry data from the physical file structure and storing the accelerator telemetry data into virtual files that are visible to application software programs that invoke the accelerator. The accelerator telemetry data describes an input/output memory management unit’s performance regarding its translation of virtual addresses to physical addresses for the accelerator.

公开(公告)号：US20230195899A1

公开(公告)日：2023-06-22

申请号：US18109837

申请日：2023-02-14

Applicant: Intel Corporation

Inventor： Naveen LAKKAKULA ,  John J. BROWNE ,  Laurent COQUEREL ,  Fei Z. WANG

IPC: G06F21/57 ,  G06F21/44 ,  G06F9/4401

CPC classification number: G06F21/572 ,  G06F21/575 ,  G06F21/44 ,  G06F9/4405 ,  G06F2221/033

Abstract: An apparatus is described. The apparatus includes a plurality of processing cores and at least one accelerator within a semiconductor chip package. The accelerator is to offload at least one task from the processing cores after boot-up of the processing cores and the accelerator. The accelerator is also to perform authentication of firmware during the boot-up. The firmware is to execute on one of the at least one accelerator.

公开(公告)号：US20220391250A1

公开(公告)日：2022-12-08

申请号：US17891916

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： John J. BROWNE ,  Chris MACNAMARA

IPC: G06F9/48 ,  G06F9/455

Abstract: Examples described herein relate to determination of per-virtualized execution environment power usage based on an identifier of a processor that executes at least two virtualized execution environments, power usage of the processor, and number of virtualized execution environments executed by the processor.

公开(公告)号：US20210320870A1

公开(公告)日：2021-10-14

申请号：US17356420

申请日：2021-06-23

Applicant: Intel Corporation

Inventor： Patrick CONNOR ,  Andrey CHILIKIN ,  Brendan RYAN ,  Chris MACNAMARA ,  John J. BROWNE ,  Krishnamurthy JAMBUR SATHYANARAYANA ,  Stephen DOYLE ,  Tomasz KANTECKI ,  Anthony KELLY ,  Ciara LOFTUS ,  Fiona TRAHE

IPC: H04L12/803 ,  G06F9/455 ,  H04L12/851 ,  H04L12/26 ,  G06F8/76

Abstract: A computing device includes an appliance status table to store at least one of reliability and performance data for one or more network functions virtualization (NFV) appliances and one or more legacy network appliances. The computing device includes a load controller to configure an Internet Protocol (IP) filter rule to select a packet for which processing of the packet is to be migrated from a selected one of the one or more legacy network appliances to a selected one of the one or more NFV appliances, and to update the appliance status table with received at least one of reliability and performance data for the one or more legacy network appliances and the one or more NFV appliances. The computing device includes a packet distributor to receive the packet, to select one of the one or more NFV appliances based at least in part on the appliance status table, and to send the packet to the selected NFV appliance. Other embodiments are described herein.

公开(公告)号：US20190215272A1

公开(公告)日：2019-07-11

申请号：US16353730

申请日：2019-03-14

Applicant: Intel Corporation

Inventor： Jasvinder SINGH ,  John J. BROWNE ,  Shobhi JAIN ,  Sunku RANGANATH ,  John O'LOUGHLIN ,  Emma L. FOLEY

IPC: H04L12/803 ,  H04L12/801 ,  H04L12/851 ,  G06F9/445

CPC classification number: H04L47/122 ,  G06F9/445 ,  H04L47/19 ,  H04L47/2408

Abstract: Examples include a method of determining a first traffic overload protection policy for a first service provided by a first virtual network function in a network of virtual network functions in a computing system and determining a second traffic overload protection policy for a second service provided by a second virtual network function in the network of virtual network functions. The method includes applying the first traffic overload protection policy to the first virtual network function and the second traffic overload protection policy to the second virtual network function, wherein the first traffic overload protection policy and the second traffic overload protection policy are different.

公开(公告)号：US20240334245A1

公开(公告)日：2024-10-03

申请号：US18737212

申请日：2024-06-07

Applicant: Intel Corporation

Inventor： John J. BROWNE ,  Andrey CHILIKIN ,  Elazar COHEN ,  Joseph HASTING ,  James CLEE ,  Jerry PIROG ,  Jamison D. WHITESELL ,  Ambalavanar ARULAMBALAM ,  Anjali Singhai JAIN ,  Andrew CUNNINGHAM ,  Ruben DAHAN

IPC: H04W28/06 ,  H04W28/02

CPC classification number: H04W28/06 ,  H04W28/0273 ,  H04W28/0289

Abstract: Examples described herein relate to a network interface device that performs: offloading processing of fragments of a packet to an accelerator; processing non-fragmented packets; and prioritizing dropping of fragments of the packet over dropping of non-fragmented packets. Offloading processing of fragments of the packet to the accelerator can include: the accelerator performing: reassembling the fragments of the packet into a first reassembly packet; and based on congestion associated with at least one of the fragments of the packet of the first reassembly packet: dropping fragments of the first reassembly packet associated with one or more flows; halting reassembly of the first reassembly packet; and forwarding a second packet to a host system, wherein the second packet indicates that congestion occurred, identifies one or more impacted flows, and indicates a number of dropped packet fragments.