公开(公告)号：US20200371136A1

公开(公告)日：2020-11-26

申请号：US16992947

申请日：2020-08-13

Applicant: Intel Corporation

Inventor： Paul J. Diglio ,  Joseph F. Walczyk

IPC: G01R1/073 ,  G01R1/04 ,  G01R31/28

Abstract: Planar error between a probe card and a semiconductor wafer may be reduced with a low-profile gimbal platform. The low-profile gimbal platform may be coupled between a probe card and a tester head. The low-profiled gimbal platform includes a number of linear actuators and pistons that are used to perform high-precision in situ planarity adjustments to the probe card to achieve co-planarity between the probe card and the semiconductor wafer. The in situ planarity adjustments may reduce the likelihood of malfunctions due to misalignment of the probe card.

公开(公告)号：US10775414B2

公开(公告)日：2020-09-15

申请号：US15721331

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Paul J. Diglio ,  Joseph F. Walczyk

IPC: G01R1/073 ,  G01R31/28 ,  G01R1/04

Abstract: Planar error between a probe card and a semiconductor wafer may be reduced with a low-profile gimbal platform. The low-profile gimbal platform may be coupled between a probe card and a tester head. The low-profiled gimbal platform includes a number of linear actuators and pistons that are used to perform high-precision in situ planarity adjustments to the probe card to achieve co-planarity between the probe card and the semiconductor wafer. The in situ planarity adjustments may reduce the likelihood of malfunctions due to misalignment of the probe card.

公开(公告)号：US11674980B2

公开(公告)日：2023-06-13

申请号：US16992947

申请日：2020-08-13

Applicant: Intel Corporation

Inventor： Paul J. Diglio ,  Joseph F. Walczyk

IPC: G01R1/073 ,  G01R1/04 ,  G01R31/28

CPC classification number: G01R1/07364 ,  G01R1/04 ,  G01R1/07342 ,  G01R31/2831 ,  G01R31/2891

Abstract: Planar error between a probe card and a semiconductor wafer may be reduced with a low-profile gimbal platform. The low-profile gimbal platform may be coupled between a probe card and a tester head. The low-profiled gimbal platform includes a number of linear actuators and pistons that are used to perform high-precision in situ planarity adjustments to the probe card to achieve co-planarity between the probe card and the semiconductor wafer. The in situ planarity adjustments may reduce the likelihood of malfunctions due to misalignment of the probe card.

公开(公告)号：US20230095039A1

公开(公告)日：2023-03-30

申请号：US17478337

申请日：2021-09-17

Applicant: Intel Corporation

Inventor： Srikant Nekkanty ,  Pooya Tadayon ,  Xavier F. Brun ,  Wesley B. Morgan ,  John M. Heck ,  Joseph F. Walczyk ,  Paul J. Diglio

IPC: G02B6/26

Abstract: Technologies for optical coupling to photonic integrated circuit (PIC) dies are disclosed. In the illustrative embodiment, a lens assembly with one or more lenses is positioned to collimate light coming out of one or more waveguides in the PIC die. Part of the illustrative lens assembly extends above a top surface of the PIC die and is in contact with the PIC die. The top surface of the PIC die establishes the vertical positioning of the lens assembly. In the illustrative embodiment, the lens assembly is positioned at least partially inside a cavity defined within the PIC die, which allows the lens assembly to be integrated at the wafer level, before singulation into individual dies.

公开(公告)号：US20160178663A1

公开(公告)日：2016-06-23

申请号：US14581508

申请日：2014-12-23

Applicant: INTEL CORPORATION

Inventor： Mohanraj Prabhugoud ,  Youngseok Oh ,  Joseph F. Walczyk ,  Todd P. Albertson

IPC: G01R1/04 ,  G01R1/073 ,  G01R1/067

CPC classification number: G01R1/07357 ,  G01R1/0466 ,  G01R1/0483

Abstract: A test die contactor is described with a formed wire probe interconnect. In one example the contactor includes a plurality of wire probes formed to be resilient against longitudinal pressure, a first aligner proximate one end of the wire probes having a first plurality of holes through which the wire probes extend, the first alignment layer to align the wire probes to contact pads of a text fixture, a second aligner proximate the other end of the wire probes having a second plurality of holes through the wire probes extend, the second alignment layer to align the wire probes to contact pads of a device under test, and an insulating layer between the first and the second aligner through which the wire probes extend to hold the wire probes when compressed by longitudinal pressure.

Abstract translation: 使用形成的导线探针互连来描述测试模具接触器。 在一个示例中，接触器包括形成为抵抗纵向压力弹性的多个线探针，靠近线探头的一端的第一对准器具有第一多个孔，线探针延伸穿过该第一多个孔，第一对准层对准线 探针到文本夹具的接触垫，靠近导线探针的另一端的第二对准器具有穿过线探头的第二多个孔延伸，第二对准层将线探针对准待测器件的接触垫， 以及在第一和第二对准器之间的绝缘层，当通过纵向压力压缩时，线探针延伸通过该绝缘层保持线探头。