公开(公告)号：US20190042356A1

公开(公告)日：2019-02-07

申请号：US16145983

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Lei CHEN ,  Xin GUO ,  Shu-Jen LEE ,  Chu-hsiang TENG ,  Scott NELSON ,  Donia SEBASTIAN

IPC: G06F11/10 ,  G11C16/34 ,  G11C16/26

CPC classification number: G06F11/1012 ,  G11C16/26 ,  G11C16/3431 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: Examples described herein can be used to reduce a number of re-read operations and potentially avoid data recovery operations, which can be time consuming. A determination can be made of a read voltage to apply during an operation to cause a read of data stored in a region of a memory device. The region of the memory device can be read using the read voltage. If the region is not successfully read, then an error level indication can be measured and a second read voltage can be determined for a re-read operation. If the re-read operation is not successful, then a second error level indication can be measured for the re-read operation. A third read voltage can be selected based on the change from the error level indication to the second error level indication.

公开(公告)号：US20220091934A1

公开(公告)日：2022-03-24

申请号：US17544085

申请日：2021-12-07

Applicant: Intel Corporation

Inventor： Lei CHEN ,  Liyang LING ,  Xiaodong QIU ,  Yong JIANG

IPC: G06F11/10 ,  G06F11/07 ,  G06F3/06

Abstract: An embodiment of an electronic apparatus may comprise one or more substrates and a controller coupled to the one or more substrates, the controller including circuitry to identify failed memory regions in a memory by a rank, bank, and device associated with the failed memory region, and provide recovery for failed memory regions in three or more banks of a first rank of the memory or three or more devices of the first rank of the memory by virtual lock step device data correction with one or more other ranks of the memory. Other embodiments are disclosed and claimed.

公开(公告)号：US20200027503A1

公开(公告)日：2020-01-23

申请号：US16586214

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Lei CHEN ,  Yogesh B. WAKCHAURE ,  Aliasgar S. MADRASWALA ,  Xin GUO ,  Cole UHLMAN

IPC: G11C11/56 ,  G06F3/06 ,  G11C16/08

Abstract: A method and apparatus to reduce read retry operations in a NAND Flash memory is provided. To reduce the number of read retries for future reads, a word line group is assigned an optimal read voltage, the reference voltage that results in eliminating the read error for the word line is selected as the optimal read voltage (also referred to as a “sticky voltage”) for the word line group to be used for a next read of the page. An optimal read voltage per word line group for the page per NAND Flash memory die is stored in the lookup table. Storing an optimal read voltage per word line group instead of per die reduces the number of read retries.

公开(公告)号：US20160065934A1

公开(公告)日：2016-03-03

申请号：US14576792

申请日：2014-12-19

Applicant: INTEL CORPORATION

Inventor： Krishna KAZA ,  Vivek KUMAR ,  Kabeer R. MANCHANDA ,  Sreenivasulu GOSANGI ,  Jianxu ZHENG ,  Lei CHEN ,  Wen WANG

IPC: H04N13/00 ,  H04N13/02

CPC classification number: H04N13/296 ,  G01B11/245 ,  H04N5/2258 ,  H04N13/271

Abstract: An imaging architecture is described for a depth camera mode with mode switching. In one example, an imaging device has a primary camera to capture an image of a scene, a secondary camera to capture an image of the same scene, a third camera to capture an image of a second scene, a processor having a first port coupled to the primary camera to receive images from the primary camera and a second port to receive images, and a multiplexer coupled to the secondary camera and to the third camera to receive the captured images and to alternately couple the secondary camera or the third camera to the second port of the processor.

Abstract translation: 描述了具有模式切换的深度相机模式的成像架构。 在一个示例中，成像装置具有用于捕获场景的图像的主相机，用于捕获相同场景的图像的辅助照相机，用于捕获第二场景的图像的第三相机，具有耦合的第一端口的处理器 主相机接收来自主相机的图像和用于接收图像的第二端口，以及耦合到次相机和第三相机的多路复用器以接收所捕获的图像，并且将次相机或第三相机交替耦合到 处理器的第二个端口。