公开(公告)号：US20160204787A1

公开(公告)日：2016-07-14

申请号：US14127963

申请日：2013-09-26

Applicant: INTEL CORPORATION

Inventor： Amr M. LOTFY ,  Mohamed A. ABDELSALAM ,  Mamdouh O. ABD EL-MEJEED ,  Nasser A. KURD ,  Mohamed A. ABDELMONEUM ,  Mark ELZINGA ,  Young Min PARK ,  Jagannadha R. RAPETA ,  Surya MUSUNURI

IPC: H03L7/10 ,  G04F10/00 ,  H03L7/099

CPC classification number: H03L7/105 ,  G04F10/005 ,  H03L7/085 ,  H03L7/0992 ,  H03L7/10 ,  H03L7/103 ,  H03L2207/06

Abstract: Described is an integrated circuit (IC) with a phase locked loop with capability of fast locking. The IC comprises: a node to provide a reference clock; a digitally controlled oscillator (DCO) to generate an output clock; a divider coupled to the DCO, the divider to divide the output clock and to generate a feedback clock; and control logic operable to reset the DCO and the divider, and operable to release reset in synchronization with the reference clock. An apparatus for zeroing phase error is provided which comprises a first node to provide a reference clock; a second node to provide a feedback clock; a time-to-digital converter, coupled to the first and second nodes, to measure phase error between the reference and feedback clocks; a digital loop filter; and a control unit to adjust the measured phase error, and to provide the adjusted phase error to the digital loop filter.

Abstract translation: 描述了具有锁相环的集成电路（IC），具有快速锁定能力。 IC包括：提供参考时钟的节点; 数字控制振荡器（DCO），用于产生输出时钟; 耦合到DCO的分频器，分频器分频输出时钟并产生反馈时钟; 以及控制逻辑，可操作以复位DCO和分频器，并且可操作以与参考时钟同步地释放复位。 提供了一种用于归零相位误差的装置，其包括提供参考时钟的第一节点; 提供反馈时钟的第二节点; 耦合到第一和第二节点的时间 - 数字转换器，以测量参考和反馈时钟之间的相位误差; 数字环路滤波器; 以及控制单元，用于调整所测量的相位误差，并向数字环路滤波器提供经调整的相位误差。

公开(公告)号：US20180351565A1

公开(公告)日：2018-12-06

申请号：US16057754

申请日：2018-08-07

Applicant: Intel Corporation

Inventor： Young Min PARK ,  Mark ELZINGA

IPC: H03M1/06 ,  G04F10/00

CPC classification number: H03M1/0626 ,  G04F10/005 ,  H03M1/0607

Abstract: Described is an apparatus which comprises: a time-to-digital converter (TDC) to receive a reference clock and a feedback clock, wherein the TDC is to generate a digital output code representing a time difference between the reference clock and the feedback clock; a circuitry to apply a digital code to an output of the TDC; and a node to receive the digital output code from the TDC and the digital code from the circuitry, wherein the circuitry is to monitor the digital output code and to control the TDC according to at least the monitored digital output code.