公开(公告)号：US20150082890A1

公开(公告)日：2015-03-26

申请号：US14037668

申请日：2013-09-26

Applicant: Intel Corporation

Inventor： Mondira D. PANT ,  Mohamed A. ABDELMONEUM ,  Tanay KARNIK ,  Stephen PISENTI ,  David I. POISNER ,  Rashed MAHAMEED

IPC: G01N29/24 ,  G01N29/265

CPC classification number: G01N29/265 ,  G01N2291/106 ,  G06F21/32 ,  G06F2221/2111 ,  G06K9/0002 ,  Y10T29/49005

Abstract: Methods and systems may provide for a system having a flexible substrate, an ultrasonic transducer array coupled to the flexible substrate and a processor coupled to the ultrasonic transducer array. The processor may identify a fingerprint based on a signal from the ultrasonic transducer array. The system may also include an external component having a curved profile, wherein the ultrasonic transducer array is embedded in the external component and includes a read surface that conforms to the curved profile. In one example, the external component includes a button having a function that is separate from identification of the fingerprint.

Abstract translation: 方法和系统可以提供具有柔性衬底，耦合到柔性衬底的超声换能器阵列和耦合到超声换能器阵列的处理器的系统。 处理器可以基于来自超声换能器阵列的信号识别指纹。 该系统还可以包括具有弯曲轮廓的外部部件，其中超声换能器阵列嵌入在外部部件中并且包括符合弯曲轮廓的读取表面。 在一个示例中，外部组件包括具有与指纹的识别分离的功能的按钮。

公开(公告)号：US20160204787A1

公开(公告)日：2016-07-14

申请号：US14127963

申请日：2013-09-26

Applicant: INTEL CORPORATION

Inventor： Amr M. LOTFY ,  Mohamed A. ABDELSALAM ,  Mamdouh O. ABD EL-MEJEED ,  Nasser A. KURD ,  Mohamed A. ABDELMONEUM ,  Mark ELZINGA ,  Young Min PARK ,  Jagannadha R. RAPETA ,  Surya MUSUNURI

IPC: H03L7/10 ,  G04F10/00 ,  H03L7/099

CPC classification number: H03L7/105 ,  G04F10/005 ,  H03L7/085 ,  H03L7/0992 ,  H03L7/10 ,  H03L7/103 ,  H03L2207/06

Abstract: Described is an integrated circuit (IC) with a phase locked loop with capability of fast locking. The IC comprises: a node to provide a reference clock; a digitally controlled oscillator (DCO) to generate an output clock; a divider coupled to the DCO, the divider to divide the output clock and to generate a feedback clock; and control logic operable to reset the DCO and the divider, and operable to release reset in synchronization with the reference clock. An apparatus for zeroing phase error is provided which comprises a first node to provide a reference clock; a second node to provide a feedback clock; a time-to-digital converter, coupled to the first and second nodes, to measure phase error between the reference and feedback clocks; a digital loop filter; and a control unit to adjust the measured phase error, and to provide the adjusted phase error to the digital loop filter.

Abstract translation: 描述了具有锁相环的集成电路（IC），具有快速锁定能力。 IC包括：提供参考时钟的节点; 数字控制振荡器（DCO），用于产生输出时钟; 耦合到DCO的分频器，分频器分频输出时钟并产生反馈时钟; 以及控制逻辑，可操作以复位DCO和分频器，并且可操作以与参考时钟同步地释放复位。 提供了一种用于归零相位误差的装置，其包括提供参考时钟的第一节点; 提供反馈时钟的第二节点; 耦合到第一和第二节点的时间 - 数字转换器，以测量参考和反馈时钟之间的相位误差; 数字环路滤波器; 以及控制单元，用于调整所测量的相位误差，并向数字环路滤波器提供经调整的相位误差。

公开(公告)号：US20160006443A1

公开(公告)日：2016-01-07

申请号：US14831694

申请日：2015-08-20

Applicant: Intel Corporation

Inventor： Amr M. LOTFY ,  Mohamed A. ABDELSALAM ,  Mohammed W. EL MAHALAWY ,  Nasser A. KURD ,  Mohamed A. ABDELMONEUM

IPC: H03L7/099 ,  H03L7/087

CPC classification number: H03L7/00 ,  H03K3/0315 ,  H03L7/0818 ,  H03L7/087 ,  H03L7/0992

Abstract: Described herein is apparatus and system for a digitally controlled oscillator (DCO). The apparatus comprises a voltage regulator to provide an adjustable power supply; and a DCO to generate an output clock signal, the DCO including one or more delay elements, each delay element operable to change its propagation delay via the adjustable power supply, wherein each delay element comprising an inverter with adjustable drive strength, wherein the inverter is powered by the adjustable power supply. The apparatus further comprises a digital controller to generate a first signal for instructing the voltage regulator to adjust a voltage level of the adjustable power supply.

公开(公告)号：US20150368091A1

公开(公告)日：2015-12-24

申请号：US14839743

申请日：2015-08-28

Applicant: Intel Corporation

Inventor： Rashed MAHAMEED ,  Kristen L. DORSEY ,  Mamdouh O. M M ABDELMEJEED ,  Mohamed A. ABDELMONEUM

IPC: B81B3/00 ,  B81C1/00

CPC classification number: B81B3/0051 ,  B81B3/0021 ,  B81B7/008 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2203/0145 ,  B81C1/00166 ,  B81C1/00246 ,  B81C1/00531 ,  B81C2203/0714 ,  B81C2203/0742 ,  G01C19/5733 ,  G01P15/125 ,  G01P2015/0814

Abstract: A MEMS device, such as an accelerometer or gyroscope, fabricated in interconnect metallization compatible with a CMOS microelectronic device. In embodiments, a proof mass has a first body region utilizing a thick metal layer that is separated from a thin metal layer. The thick metal layer has a film thickness that is significantly greater than that of the thin metal layer for increased mass. The proof mass further includes a first sensing structure comprising the thin metal layer, but lacking the thick metal layer for small feature sizes and increased capacitive coupling to a surrounding frame that includes a second sensing structure comprising the thin metal layer, but also lacking the thick metal layer. In further embodiments, the frame is released and includes regions with the thick metal layer to better match film stress-induced static deflection of the proof mass.

Abstract translation: MEMS器件，例如加速度计或陀螺仪，其制造在与CMOS微电子器件兼容的互连金属化中。 在实施例中，检验质量体具有利用与金属薄层分离的厚金属层的第一体区。 厚金属层的膜厚度明显大于金属层的厚度，以增加质量。 检测质量还包括第一感测结构，其包括薄金属层，但是缺少用于小特征尺寸的厚金属层，并且增加与周围框架的电容耦合，其包括包含薄金属层的第二感测结构，而且还缺少厚的 金属层。 在另外的实施例中，框架被释放并且包括具有较厚金属层的区域以更好地匹配膜应力引起的证明块的静态偏转。