公开(公告)号：US20160266603A1

公开(公告)日：2016-09-15

申请号：US14917928

申请日：2013-12-03

Applicant: INTEL CORPORATION

Inventor： Surya MUSUNURI ,  Jagannadha R. RAPETA ,  L. Mark ELZINGA ,  Young Min PARK ,  Robert FULTON

IPC: G06F1/08 ,  G06F13/36 ,  G06F13/40

CPC classification number: G06F1/08 ,  G06F13/36 ,  G06F13/4068 ,  H03L7/183 ,  H03L2207/50

Abstract: Described is an apparatus for over-clocking or under-clocking, the apparatus comprises: a locked loop (e.g., phase locked loop or frequency locked loop) having a feedback divider, the locked loop to receive a reference clock and to compare it with a feedback clock which is output from the feedback divider, and to generate an output clock; a post locked loop divider, coupled to the locked loop, to receive the output clock and to generate a base clock for other logic units; and a control logic to adjust first and second divider ratios for the feedback divider and the post locked loop divider respectively for over-clocking or under-clocking the base clock such that the locked loop remains locked while being over-clocked or under-clocked.

Abstract translation: 描述了一种用于超频或欠时钟的装置，该装置包括：具有反馈分频器的锁定环（例如，锁相环或锁频环），锁定环接收参考时钟并将其与 反馈分频器输出的反馈时钟，并产生输出时钟; 耦合到锁定环的锁相环分压器，以接收输出时钟并产生用于其它逻辑单元的基本时钟; 以及用于分别用于反馈分频器和后锁相环分频器的第一和第二分频比的控制逻辑，用于超频或欠时钟基本时钟，使得锁定的环路在被超频或欠频的情况下保持锁定。

公开(公告)号：US20160204787A1

公开(公告)日：2016-07-14

申请号：US14127963

申请日：2013-09-26

Applicant: INTEL CORPORATION

Inventor： Amr M. LOTFY ,  Mohamed A. ABDELSALAM ,  Mamdouh O. ABD EL-MEJEED ,  Nasser A. KURD ,  Mohamed A. ABDELMONEUM ,  Mark ELZINGA ,  Young Min PARK ,  Jagannadha R. RAPETA ,  Surya MUSUNURI

IPC: H03L7/10 ,  G04F10/00 ,  H03L7/099

CPC classification number: H03L7/105 ,  G04F10/005 ,  H03L7/085 ,  H03L7/0992 ,  H03L7/10 ,  H03L7/103 ,  H03L2207/06

Abstract: Described is an integrated circuit (IC) with a phase locked loop with capability of fast locking. The IC comprises: a node to provide a reference clock; a digitally controlled oscillator (DCO) to generate an output clock; a divider coupled to the DCO, the divider to divide the output clock and to generate a feedback clock; and control logic operable to reset the DCO and the divider, and operable to release reset in synchronization with the reference clock. An apparatus for zeroing phase error is provided which comprises a first node to provide a reference clock; a second node to provide a feedback clock; a time-to-digital converter, coupled to the first and second nodes, to measure phase error between the reference and feedback clocks; a digital loop filter; and a control unit to adjust the measured phase error, and to provide the adjusted phase error to the digital loop filter.

Abstract translation: 描述了具有锁相环的集成电路（IC），具有快速锁定能力。 IC包括：提供参考时钟的节点; 数字控制振荡器（DCO），用于产生输出时钟; 耦合到DCO的分频器，分频器分频输出时钟并产生反馈时钟; 以及控制逻辑，可操作以复位DCO和分频器，并且可操作以与参考时钟同步地释放复位。 提供了一种用于归零相位误差的装置，其包括提供参考时钟的第一节点; 提供反馈时钟的第二节点; 耦合到第一和第二节点的时间 - 数字转换器，以测量参考和反馈时钟之间的相位误差; 数字环路滤波器; 以及控制单元，用于调整所测量的相位误差，并向数字环路滤波器提供经调整的相位误差。