公开(公告)号：US12107044B2

公开(公告)日：2024-10-01

申请号：US16389672

申请日：2019-04-19

Applicant: Intel Corporation

Inventor： Marie Krysak ,  Kevin L. Lin ,  Robert Bristol ,  Charles H. Wallace

IPC: H01L23/528 ,  H01L21/027 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/0273 ,  H01L21/76816 ,  H01L21/76877

Abstract: Embodiments include a substrate and a method of forming the substrate. A substrate includes an interlayer dielectric and conductive traces in the interlayer dielectric (ILD). The conductive traces may include a first conductive trace surrounded by a second and third conductive traces. The substrate also includes a photoresist block in a region of the ILD. The region may be directly surrounded by the ILD and first conductive trace, and the photoresist block may be between the first conductive trace. The photoresist block may have a top surface that is substantially coplanar to top surfaces of the ILD and conductive traces. The photoresist block may have a width substantially equal to a width of the conductive traces. The photoresist block may be in the first conductive trace and between the second and third conductive traces. The photoresist block may include a metal oxide core embedded with organic ligands.

公开(公告)号：US12002754B2

公开(公告)日：2024-06-04

申请号：US16911879

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： Hui Jae Yoo ,  Kevin L. Lin

IPC: H01L23/528 ,  H01L21/311 ,  H01L21/32 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/31116 ,  H01L21/32 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5286 ,  H01L23/53228

Abstract: Integrated circuit metallization lines having a planar top surface but different vertical heights, for example to control intra-layer resistance/capacitance of integrated circuit interconnect. A hardmask material layer may be inserted between two thicknesses of dielectric material that are over a via metallization. Following deposition of the hardmask material layer, trench openings may be patterned through the hardmask layer to define where line metallization will have a greater height. Following the deposition of a thickness of dielectric material over the hardmask material layer, a trench pattern may be etched through the uppermost thickness of dielectric material, exposing the hardmask material layer wherever the trench does not coincide with an opening in the hardmask material layer. The trench etch may be retarded where the hardmask material layer is exposed, resulting to trenches of differing depth. Trenches of differing depth may be filled with metallization and then planarized.

公开(公告)号：US11189790B2

公开(公告)日：2021-11-30

申请号：US16320789

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Kevin L. Lin ,  Sarah E. Atanasov ,  Kevin P. O'Brien ,  Robert L. Bristol

IPC: H01L45/00 ,  H01L27/24

Abstract: Spacer-based patterning for tight-pitch and low-variability random access memory (RAM) bit cells, and the resulting structures, are described. In an example, a semiconductor structure includes a substrate having a top layer. An array of non-volatile random access memory (RAM) bit cells is disposed on the top layer of the substrate. The array of non-volatile RAM bit cells includes columns of non-volatile RAM bit cells along a first direction and rows of non-volatile RAM bit cells along a second direction orthogonal to the first direction. A plurality of recesses is in the top layer of the substrate, along the first direction between columns of the array of non-volatile RAM bit cells.

公开(公告)号：US11011481B2

公开(公告)日：2021-05-18

申请号：US16461546

申请日：2016-12-29

Applicant: Intel Corporation

Inventor： Kevin L. Lin ,  James M. Blackwell

IPC: H01L23/64 ,  H01C10/16 ,  H01L21/3213 ,  H01L23/522 ,  H01L23/525 ,  H01L27/06 ,  H01L49/02 ,  H03K19/08

Abstract: In an example, there is disclosed a configurable impedance element, having: a first impedance network including a plurality of series impedance elements and providing an initial impedance; a trim impedance network parallel to the first impedance network, including a plurality of corresponding impedance elements to the impedance elements of the first impedance network; and antifuses between the impedance elements of the first impedance network and their corresponding impedance elements of the trim network. There is also disclosed an integrated circuit including the impedance element, and a method of manufacturing and configuring the impedance element.

公开(公告)号：US20200098629A1

公开(公告)日：2020-03-26

申请号：US16465526

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： Kevin L. Lin ,  Tayseer Mahdi ,  Jessica M. Torres ,  Jeffery D. Bielefeld ,  Marie Krysak ,  James M. Blackwell

IPC: H01L21/768

Abstract: In an example, there is disclosed an integrated circuit, having: a first layer having a dielectric, a first conductive interconnect and a second conductive interconnect; a second layer having a third conductive interconnect; a conductive via between the first layer and the second layer to electrically couple the second conductive interconnect to the third conductive interconnect; and an etch-resistant plug disposed vertically between the first layer and second layer and disposed to prevent the via from electrically shorting to the first conductive interconnect.

公开(公告)号：US12156473B2

公开(公告)日：2024-11-26

申请号：US16631681

申请日：2017-09-20

Applicant: Intel Corporation

Inventor： Kevin L. Lin ,  Nicholas James Harold McKubre ,  Han Wui Then

IPC: H01L41/09 ,  H01F27/24 ,  H01F27/30 ,  H01L49/02 ,  H10N30/20

Abstract: Disclosed herein are inductor/core assemblies for integrated circuits (ICs), as well as related structures, methods, and devices. In some embodiments, an IC structure may include an inductor and a magnetic core in an interior of the inductor. The magnetic core may be movable perpendicular to a plane of the inductor.

公开(公告)号：US20240304549A1

公开(公告)日：2024-09-12

申请号：US18668042

申请日：2024-05-17

Applicant: Intel Corporation

Inventor： Hui Jae Yoo ,  Kevin L. Lin

IPC: H01L23/528 ,  H01L21/311 ,  H01L21/32 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/31116 ,  H01L21/32 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5286 ,  H01L23/53228

Abstract: Integrated circuit metallization lines having a planar top surface but different vertical heights, for example to control intra-layer resistance/capacitance of integrated circuit interconnect. A hardmask material layer may be inserted between two thicknesses of dielectric material that are over a via metallization. Following deposition of the hardmask material layer, trench openings may be patterned through the hardmask layer to define where line metallization will have a greater height. Following the deposition of a thickness of dielectric material over the hardmask material layer, a trench pattern may be etched through the uppermost thickness of dielectric material, exposing the hardmask material layer wherever the trench does not coincide with an opening in the hardmask material layer. The trench etch may be retarded where the hardmask material layer is exposed, resulting to trenches of differing depth. Trenches of differing depth may be filled with metallization and then planarized.

公开(公告)号：US11955377B2

公开(公告)日：2024-04-09

申请号：US17568648

申请日：2022-01-04

Applicant: Intel Corporation

Inventor： Kevin L. Lin ,  Robert L Bristol ,  James M. Blackwell ,  Rami Hourani ,  Marie Krysak

IPC: H01L21/311 ,  H01L21/027 ,  H01L21/768

CPC classification number: H01L21/76816 ,  H01L21/0273 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76825 ,  H01L21/76877 ,  H01L21/76897

Abstract: Approaches based on differential hardmasks for modulation of electrobucket sensitivity for semiconductor structure fabrication, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for an integrated circuit includes forming a hardmask layer above an inter-layer dielectric (ILD) layer formed above a substrate. A plurality of dielectric spacers is formed on the hardmask layer. The hardmask layer is patterned to form a plurality of first hardmask portions. A plurality of second hardmask portions is formed alternating with the first hardmask portions. A plurality of electrobuckets is formed on the alternating first and second hardmask portions and in openings between the plurality of dielectric spacers. Select ones of the plurality of electrobuckets are exposed to a lithographic exposure and removed to define a set of via locations.

公开(公告)号：US11626451B2

公开(公告)日：2023-04-11

申请号：US16442767

申请日：2019-06-17

Applicant: INTEL CORPORATION

Inventor： Emily Walker ,  Carl H. Naylor ,  Kaan Oguz ,  Kevin L. Lin ,  Tanay Gosavi ,  Christopher J. Jezewski ,  Chia-Ching Lin ,  Benjamin W. Buford ,  Dmitri E. Nikonov ,  John J. Plombon ,  Ian A. Young ,  Noriyuki Sato

IPC: H01L27/22 ,  H01L43/12 ,  G11C11/16 ,  H01L43/08 ,  H01L43/02 ,  H01L43/10

Abstract: A magnetic memory device comprising a plurality of memory cells is disclosed. The memory device includes an array of memory cells where each memory cell includes a first material layer having a ferromagnetic material, a second material layer having ruthenium, and a third material layer having bismuth and/or antimony. The second material layer is sandwiched between the first material layer and the third material in a stacked configuration.

公开(公告)号：US11373950B2

公开(公告)日：2022-06-28

申请号：US17110215

申请日：2020-12-02

Applicant: Intel Corporation

Inventor： Richard E. Schenker ,  Robert L. Bristol ,  Kevin L. Lin ,  Florian Gstrein ,  James M. Blackwell ,  Marie Krysak ,  Manish Chandhok ,  Paul A. Nyhus ,  Charles H. Wallace ,  Curtis W. Ward ,  Swaminathan Sivakumar ,  Elliot N. Tan

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L27/088 ,  H01L29/78

Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.