公开(公告)号：US09552316B2

公开(公告)日：2017-01-24

申请号：US14229870

申请日：2014-03-29

Applicant: INTEL CORPORATION

Inventor： Nathaniel L. Desimone ,  Robert E. Gough ,  Sean C. Dardis

IPC: G06F13/38 ,  G06F9/44 ,  G06F13/42

CPC classification number: G06F9/4411 ,  G06F9/4406 ,  G06F13/382 ,  G06F13/385 ,  G06F13/387 ,  G06F13/4221 ,  G06F13/4282

Abstract: Techniques for adaptive interface support are described. In one embodiment, for example, an apparatus may comprise logic, at least a portion of which is in hardware, the logic to execute a basic input/output system (BIOS), determine a respective impedance state for each of one or more pins in an M.2 physical interface, determine an interface type for a peripheral device coupled with the M.2 physical interface based on the impedance states for the one or more pins, and control an operational state of the peripheral device during execution of the BIOS, based on the interface type for the peripheral device. Other embodiments are described and claimed.

Abstract translation: 描述了自适应接口支持的技术。 在一个实施例中，例如，设备可以包括其硬件中的至少一部分的逻辑，用于执行基本输入/输出系统（BIOS）的逻辑，为每个的一个或多个引脚确定相应的阻抗状态 M.2物理接口，基于一个或多个引脚的阻抗状态确定与M.2物理接口耦合的外围设备的接口类型，并且在BIOS的执行期间控制外围设备的操作状态， 基于外围设备的接口类型。 描述和要求保护其他实施例。

公开(公告)号：US09965293B2

公开(公告)日：2018-05-08

申请号：US15394922

申请日：2016-12-30

Applicant: INTEL CORPORATION

Inventor： Nathaniel L. Desimone ,  Robert E. Gough ,  Sean C. Dardis

IPC: G06F9/44 ,  G06F13/38 ,  G06F13/42

CPC classification number: G06F9/4411 ,  G06F9/4406 ,  G06F13/382 ,  G06F13/385 ,  G06F13/387 ,  G06F13/4221 ,  G06F13/4282

Abstract: Techniques for adaptive interface support are described. In one embodiment, for example, an apparatus may comprise logic, at least a portion of which is in hardware, the logic to execute a basic input/output system (BIOS), determine a respective impedance state for each of one or more pins in an M.2 physical interface, determine an interface type for a peripheral device coupled with the M.2 physical interface based on the impedance states for the one or more pins, and control an operational state of the peripheral device during execution of the BIOS, based on the interface type for the peripheral device. Other embodiments are described and claimed.

公开(公告)号：US20170346596A1

公开(公告)日：2017-11-30

申请号：US15166871

申请日：2016-05-27

Applicant: Intel Corporation

Inventor： Nathaniel L. Desimone ,  Theodore Zale Schoenborn ,  Earl Jeffrey Wight ,  Bryan Spry ,  Jorge Garcia Forteza ,  Sean Robert Graham ,  Duane Heller

IPC: H04L1/00 ,  G06F11/30 ,  G06F13/42 ,  H04L12/26

CPC classification number: H04L1/0034 ,  G06F11/221 ,  G06F11/24 ,  G06F11/3051 ,  G06F11/3062 ,  G06F13/4282 ,  H04L25/03885 ,  H04L43/087

Abstract: Aspects of the embodiments are directed to systems, methods, and apparatuses to determine transmission equalization coefficients (TxEQs) for one or more lanes of a high speed serial link. Embodiments include determining a jitter tolerance for each TxEQ of a plurality of TxEQs for a lane of the link. The jitter tolerance for each TxEQ for the lane is based on a level of jitter induced on the lane to detect a number of errors on the lane; determining a voltage (VOC) margin for each TxEQ for the lane, wherein the voltage margin for the lane is based on a voltage corners test applied to the lane to detect a number of errors on the lane at a high voltage point and a low voltage point; determining a TxEQ that provides maximum jitter tolerance and based on the determined lowest voltage margin; and using the TxEQ for the lane during operation.