公开(公告)号：US20180164873A1

公开(公告)日：2018-06-14

申请号：US15374684

申请日：2016-12-09

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Doron Rajwan ,  Tal Kuzi ,  Dean Mulla ,  Ariel Szapiro ,  Nir Tell

IPC: G06F1/32 ,  G06F1/26

CPC classification number: G06F1/3296 ,  G06F1/3206 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/172

Abstract: A parallel multi-step power management flow apparatus and method for using the same are disclosed. In one embodiment, an integrated circuit comprises a plurality of processing entities to execute operations, a power controller coupled to the plurality of processing entities to control power management for the plurality of processing entities, and a plurality of agents, where each of the plurality of agents is operable to perform a power control flow for one of the processing entities by separately scheduling, using a scheduler, and executing a plurality of power control flow phases in response to a plurality of requests received from the power controller, and each agent is operable to send a plurality of acknowledgements, one acknowledgement for each phase, upon completion of the plurality of power control flow phases.

公开(公告)号：US10365707B2

公开(公告)日：2019-07-30

申请号：US15374684

申请日：2016-12-09

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Doron Rajwan ,  Tal Kuzi ,  Dean Mulla ,  Ariel Szapiro ,  Nir Tell

IPC: G06F1/32 ,  G06F1/3296 ,  G06F1/3206 ,  G06F1/324

Abstract: A parallel multi-step power management flow apparatus and method for using the same are disclosed. In one embodiment, an integrated circuit comprises a plurality of processing entities to execute operations, a power controller coupled to the plurality of processing entities to control power management for the plurality of processing entities, and a plurality of agents, where each of the plurality of agents is operable to perform a power control flow for one of the processing entities by separately scheduling, using a scheduler, and executing a plurality of power control flow phases in response to a plurality of requests received from the power controller, and each agent is operable to send a plurality of acknowledgements, one acknowledgement for each phase, upon completion of the plurality of power control flow phases.

公开(公告)号：US20210096867A1

公开(公告)日：2021-04-01

申请号：US16586715

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Nir Tell ,  Shahar Sandor ,  Amotz Yagev ,  Michael Hermnoy ,  Sagie Yakov Goldenberg ,  Lihu Rappoport

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/54

Abstract: A system is provided that includes an instruction buffer that stores bytes representative of one or more macroinstructions and instruction length decoder circuitry. The instruction length decoder circuitry includes a non-sequential first multiplexer circuitry having first input lines receiving a first input data representative of a speculative length of a first macroinstruction of the macroinstructions, and first selector that selects from the first input lines via a one-hot selector vector. The instruction length decoder circuitry also includes a first output line communicatively coupled to second selector, wherein the first output line causes the selector to select from a second input data representative of a first location of a first ending byte for the first macroinstruction with respect to a value x. The first multiplexer circuitry and the second selector may output start and end byte locations for the macroinstructions.

公开(公告)号：US20210342134A1

公开(公告)日：2021-11-04

申请号：US17033751

申请日：2020-09-26

Applicant: Intel Corporation

Inventor： Ahmad Yasin ,  Lihu Rappoport ,  Jared W. Stark ,  Jeffrey Baxter ,  Israel Diamand ,  Pavel Fridman ,  Ibrahim Hur ,  Nir Tell

IPC: G06F8/41

Abstract: Embodiments of apparatuses, methods, and systems for code prefetching are described. In an embodiment, an apparatus includes an instruction decoder, load circuitry, and execution circuitry. The instruction decoder is to decode a code prefetch instruction. The code prefetch instruction is to specify a first instruction to be prefetched. The load circuitry to prefetch the first instruction in response to the decoded code prefetch instruction. The execution circuitry is to execute the first instruction at a fetch stage of a pipeline.

公开(公告)号：US11086627B2

公开(公告)日：2021-08-10

申请号：US16586715

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Nir Tell ,  Shahar Sandor ,  Amotz Yagev ,  Michael Hermony ,  Sagie Yakov Goldenberg ,  Lihu Rappoport

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/54

Abstract: A system is provided that includes an instruction buffer that stores bytes representative of one or more macroinstructions and instruction length decoder circuitry. The instruction length decoder circuitry includes a non-sequential first multiplexer circuitry having first input lines receiving a first input data representative of a speculative length of a first macroinstruction of the macroinstructions, and first selector that selects from the first input lines via a one-hot selector vector. The instruction length decoder circuitry also includes a first output line communicatively coupled to second selector, wherein the first output line causes the selector to select from a second input data representative of a first location of a first ending byte for the first macroinstruction with respect to a value x. The first multiplexer circuitry and the second selector may output start and end byte locations for the macroinstructions.

公开(公告)号：US11016556B2

公开(公告)日：2021-05-25

申请号：US16513267

申请日：2019-07-16

Applicant: INTEL CORPORATION

Inventor： Alexander Gendler ,  Doron Rajwan ,  Tal Kuzi ,  Dean Mulla ,  Ariel Szapiro ,  Nir Tell

IPC: G06F1/32 ,  G06F1/3296 ,  G06F1/3206 ,  G06F1/324

Abstract: A parallel multi-step power management flow apparatus and method for using the same are disclosed. In one embodiment, an integrated circuit comprises a plurality of processing entities to execute operations, a power controller coupled to the plurality of processing entities to control power management for the plurality of processing entities, and a plurality of agents, where each of the plurality of agents is operable to perform a power control flow for one of the processing entities by separately scheduling, using a scheduler, and executing a plurality of power control flow phases in response to a plurality of requests received from the power controller, and each agent is operable to send a plurality of acknowledgements, one acknowledgement for each phase, upon completion of the plurality of power control flow phases.