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    Technologies for remote networked accelerators
    1.
    发明授权
    Technologies for remote networked accelerators 有权

    公开(公告)号：US10970246B2

    公开(公告)日：2021-04-06

    申请号：US16402507

    申请日：2019-05-03

    Applicant: Intel Corporation

    Inventor： Paul H. Dormitzer ,  Susanne M. Balle ,  Sujoy Sen ,  Evan Custodio

    IPC: G06F15/16 ,  G06F15/173 ,  G06F13/42

    Abstract: Technologies for network interface controllers (NICs) include a computing device having a NIC coupled to a root FPGA via an I/O link. The root FPGA is further coupled to multiple worker FPGAs by a serial link with each worker FPGA. The NIC may receive a remote direct memory access (RDMA) message from a remote host and send the RDMA message to the root FPGA via the I/O link. The root FPGA determines a target FPGA based on a memory address of the RDMA message. Each FPGA is associated with a part of a unified address space. If the target FPGA is a worker FPGA, the root FPGA sends the RDMA message to the worker FPGA via the corresponding serial link, and the worker FPGA processes the RDMA message. If the root FPGA is the target, the root FPGA may process the RDMA message. Other embodiments are described and claimed.

    Technologies for facilitating remote memory requests in accelerator devices
    2.
    发明授权
    Technologies for facilitating remote memory requests in accelerator devices 有权

    公开(公告)号：US10949362B2

    公开(公告)日：2021-03-16

    申请号：US16456929

    申请日：2019-06-28

    Applicant: Intel Corporation

    Inventor： Susanne M. Balle ,  Evan Custodio ,  Paul H. Dormitzer ,  Narayan Ranganathan

    IPC: G06F13/16 ,  G06F3/06 ,  G06F13/40 ,  G06F21/60

    Abstract: Technologies for facilitating remote memory requests in accelerator devices are disclosed. The accelerator device includes circuitry to receive, from a kernel of the present accelerator device, a request through an application programming interface exposed to a high level software language in which the kernel of the present accelerator device is implemented, to establish a logical communication path between the kernel of the present accelerator device and a target accelerator device kernel, based on one or more physical communication paths. The communication protocol supported by the accelerator device may allow kernels operating on the accelerator device to send memory requests for memory locations at remote devices, with the communication protocol performing all of the operations necessary to carry out the memory request.

    TECHNOLOGIES FOR PROVIDING EFFICIENT ACCESS TO POOLED ACCELERATOR DEVICES
    3.
    发明申请
    TECHNOLOGIES FOR PROVIDING EFFICIENT ACCESS TO POOLED ACCELERATOR DEVICES 审中-公开

    公开(公告)号：US20190065083A1

    公开(公告)日：2019-02-28

    申请号：US15858557

    申请日：2017-12-29

    Applicant: Intel Corporation

    Inventor： Sujoy Sen ,  Susanne M. Balle ,  Narayan Ranganathan ,  Evan Custodio ,  Paul H. Dormitzer ,  Francesc Guim Bernat

    IPC: G06F3/06 ,  G06F21/62

    Abstract: Technologies for providing efficient access to pooled accelerator devices include an accelerator sled. The accelerator sled includes an accelerator device and a controller connected to the accelerator device. The controller is to provide, to a compute sled, accelerator abstraction data. The accelerator abstraction data represents the accelerator device as one or more logical devices, each logical device having one or more memory regions accessible by the compute sled, and defines an access mode usable to access each corresponding memory region. The controller is further to receive, from the compute sled, a request to perform an operation on an identified memory region of the accelerator device with a corresponding access mode. Additionally, the controller is to convert the request from a first format to a second format that is different from the second format and is usable by the accelerator device to perform the operation. Additionally, the controller is to perform, in response to the request, the operation on the identified memory region of the accelerator device with the corresponding access mode. Other embodiments are also described and claimed.

    Technologies for providing adaptive power management in an accelerator sled
    6.
    发明授权
    Technologies for providing adaptive power management in an accelerator sled 有权

    公开(公告)号：US11269395B2

    公开(公告)日：2022-03-08

    申请号：US16394646

    申请日：2019-04-25

    Applicant: Intel Corporation

    Inventor： Francesc Guim Bernat ,  Susanne M. Balle ,  Sujoy Sen ,  Evan Custodio ,  Paul H. Dormitzer

    IPC: G06F1/26 ,  G06F1/3234 ,  G06F1/20

    Abstract: Technologies for providing adaptive power management in an accelerator sled include an accelerator sled having circuitry to determine, based on (i) a total power budget for the accelerator sled, (ii) service level agreement (SLA) data indicative of a target performance of a kernel, and (iii) profile data indicative of a performance of the kernel as a function of a power utilization of the kernel, a power utilization limit for the kernel to be executed by an accelerator device on the accelerator sled. Additionally, the circuitry is to allocate the determined power utilization limit to the kernel and execute the kernel under the allocated power utilization limit.

    TECHNOLOGIES FOR PROVIDING INTER-KERNEL COMMUNICATION ABSTRACTION TO SUPPORT SCALE-UP AND SCALE-OUT
    7.
    发明申请
    TECHNOLOGIES FOR PROVIDING INTER-KERNEL COMMUNICATION ABSTRACTION TO SUPPORT SCALE-UP AND SCALE-OUT 审中-公开

    公开(公告)号：US20200341824A1

    公开(公告)日：2020-10-29

    申请号：US16395793

    申请日：2019-04-26

    Applicant: Intel Corporation

    Inventor： Susanne M. Balle ,  Evan Custodio ,  Narayan Ranganathan ,  Paul H. Dormitzer

    IPC: G06F9/54 ,  G06F9/38 ,  G06F15/173

    Abstract: Technologies for providing inter-kernel communication abstraction to support scale-up and scale-out include an accelerator device. The accelerator device includes circuitry to receive, from a kernel of the present accelerator device, a request through an application programming interface exposed to a high level software language in which the kernel of the present accelerator device is implemented, to establish a logical communication path between the kernel of the present accelerator device and a target accelerator device kernel, based on one or more physical communication paths. Additionally, the circuitry is to establish, in response to the request, the logical communication path between the kernel of the present accelerator device and the other accelerator device kernel and communicate data between the kernel of the present accelerator device and the other accelerator device kernel with a unified communication protocol that manages differences between the physical communication paths.

    TECHNOLOGIES FOR PROVIDING ADAPTIVE POWER MANAGEMENT IN AN ACCELERATOR SLED
    9.
    发明申请
    TECHNOLOGIES FOR PROVIDING ADAPTIVE POWER MANAGEMENT IN AN ACCELERATOR SLED 审中-公开

    公开(公告)号：US20200073464A1

    公开(公告)日：2020-03-05

    申请号：US16394646

    申请日：2019-04-25

    Applicant: Intel Corporation

    Inventor： Francesc Guim Bernat ,  Susanne M. Balle ,  Sujoy Sen ,  Evan Custodio ,  Paul H. Dormitzer

    IPC: G06F1/3234

    Abstract: Technologies for providing adaptive power management in an accelerator sled include an accelerator sled having circuitry to determine, based on (i) a total power budget for the accelerator sled, (ii) service level agreement (SLA) data indicative of a target performance of a kernel, and (iii) profile data indicative of a performance of the kernel as a function of a power utilization of the kernel, a power utilization limit for the kernel to be executed by an accelerator device on the accelerator sled. Additionally, the circuitry is to allocate the determined power utilization limit to the kernel and execute the kernel under the allocated power utilization limit.

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