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公开(公告)号:US10783100B2
公开(公告)日:2020-09-22
申请号:US16366504
申请日:2019-03-27
Applicant: Intel Corporation
Inventor: Matthew J. Adiletta , Brad Burres , Duane Galbi , Amit Kumar , Yadong Li , Salma Mirza , Jose Niell , Thomas E. Willis , William Duggan
Abstract: Technologies for flexible I/O endpoint acceleration include a computing device having a root complex, a soft endpoint coupled to the root complex, and an offload complex coupled to the soft endpoint. The soft endpoint establishes an emulated endpoint hierarchy based on endpoint firmware. The computing device may program the endpoint firmware. The soft endpoint receives an I/O transaction that originates from the root complex and determines whether to process the I/O transaction. The soft endpoint may process the I/O transaction or forward the I/O transaction to the offload complex. The soft endpoint may encapsulate the I/O transaction with metadata and forward the encapsulated transaction to the offload complex. The soft endpoint may store responses from the offload complex in a history buffer and retrieve the responses in response to retried I/O transactions. The I/O transaction may be a PCI Express transaction layer packet. Other embodiments are described and claimed.
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公开(公告)号:US20200021449A1
公开(公告)日:2020-01-16
申请号:US16583516
申请日:2019-09-26
Applicant: Intel Corporation
Inventor: Mrittika Ganguli , Joe Carvalho , Gary Muntz , Matthew J. Adiletta
IPC: H04L12/10 , H04L12/26 , H04L12/931
Abstract: Technologies for switch link and ply management for variable oversubscription ratios include powering up and down links of one or more network plys according to bandwidth demand, desired oversubscription ratio and/or other parameters. Telemetry data representing one or more network traffic metrics of one or more switch plies is monitored to determine respective power states of the plurality of links associated with the one or more switch plies as a function of a desired oversubscription ratio calculated based on the telemetry data. The respective power state of the plurality of links is set accordingly.
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公开(公告)号:US10085358B2
公开(公告)日:2018-09-25
申请号:US15396646
申请日:2016-12-31
Applicant: Intel Corporation
Inventor: Matthew J. Adiletta , Aaron Gorius , Myles Wilde , Michael T. Crocker
CPC classification number: H04Q11/0005 , B25J15/0014 , B65G1/0492 , G02B6/3882 , G02B6/3893 , G02B6/3897 , G02B6/4292 , G02B6/4452 , G05D23/1921 , G05D23/2039 , G06F1/183 , G06F3/061 , G06F3/0611 , G06F3/0613 , G06F3/0616 , G06F3/0619 , G06F3/0625 , G06F3/0631 , G06F3/0638 , G06F3/064 , G06F3/0647 , G06F3/0653 , G06F3/0655 , G06F3/0658 , G06F3/0659 , G06F3/0664 , G06F3/0665 , G06F3/067 , G06F3/0673 , G06F3/0679 , G06F3/0683 , G06F3/0688 , G06F3/0689 , G06F8/65 , G06F9/30036 , G06F9/3887 , G06F9/4401 , G06F9/5016 , G06F9/5044 , G06F9/505 , G06F9/5072 , G06F9/5077 , G06F9/544 , G06F11/141 , G06F11/3414 , G06F12/0862 , G06F12/0893 , G06F12/10 , G06F12/109 , G06F12/1408 , G06F13/161 , G06F13/1668 , G06F13/1694 , G06F13/4022 , G06F13/4068 , G06F13/409 , G06F13/42 , G06F13/4282 , G06F15/8061 , G06F16/9014 , G06F2209/5019 , G06F2209/5022 , G06F2212/1008 , G06F2212/1024 , G06F2212/1041 , G06F2212/1044 , G06F2212/152 , G06F2212/202 , G06F2212/401 , G06F2212/402 , G06F2212/7207 , G06Q10/06 , G06Q10/06314 , G06Q10/087 , G06Q10/20 , G06Q50/04 , G07C5/008 , G08C17/02 , G08C2200/00 , G11C5/02 , G11C5/06 , G11C7/1072 , G11C11/56 , G11C14/0009 , H03M7/30 , H03M7/3084 , H03M7/3086 , H03M7/40 , H03M7/4031 , H03M7/4056 , H03M7/4081 , H03M7/6005 , H03M7/6023 , H04B10/25 , H04B10/2504 , H04L9/0643 , H04L9/14 , H04L9/3247 , H04L9/3263 , H04L12/2809 , H04L29/12009 , H04L41/024 , H04L41/046 , H04L41/0813 , H04L41/082 , H04L41/0896 , H04L41/12 , H04L41/145 , H04L41/147 , H04L41/5019 , H04L43/065 , H04L43/08 , H04L43/0817 , H04L43/0876 , H04L43/0894 , H04L43/16 , H04L45/02 , H04L45/52 , H04L47/24 , H04L47/38 , H04L47/765 , H04L47/782 , H04L47/805 , H04L47/82 , H04L47/823 , H04L49/00 , H04L49/15 , H04L49/25 , H04L49/357 , H04L49/45 , H04L49/555 , H04L67/02 , H04L67/10 , H04L67/1004 , H04L67/1008 , H04L67/1012 , H04L67/1014 , H04L67/1029 , H04L67/1034 , H04L67/1097 , H04L67/12 , H04L67/16 , H04L67/306 , H04L67/34 , H04L69/04 , H04L69/329 , H04Q1/04 , H04Q11/00 , H04Q11/0003 , H04Q11/0062 , H04Q11/0071 , H04Q2011/0037 , H04Q2011/0041 , H04Q2011/0052 , H04Q2011/0073 , H04Q2011/0079 , H04Q2011/0086 , H04Q2213/13523 , H04Q2213/13527 , H04W4/023 , H04W4/80 , H05K1/0203 , H05K1/181 , H05K5/0204 , H05K7/1418 , H05K7/1421 , H05K7/1422 , H05K7/1442 , H05K7/1447 , H05K7/1461 , H05K7/1485 , H05K7/1487 , H05K7/1489 , H05K7/1491 , H05K7/1492 , H05K7/1498 , H05K7/2039 , H05K7/20709 , H05K7/20727 , H05K7/20736 , H05K7/20745 , H05K7/20836 , H05K13/0486 , H05K2201/066 , H05K2201/10121 , H05K2201/10159 , H05K2201/10189 , Y02D10/14 , Y02D10/151 , Y02P90/30 , Y04S10/54 , Y10S901/01
Abstract: A sled for operation in a corresponding rack of a data center includes a chassis-less circuit board substrate having one or more physical resources coupled to a top side of the chassis-less circuit board and one or more memory devices coupled to a bottom side of the chassis-less circuit board. The sled does not include a housing or chassis and is opened to the local environment. In the illustrative embodiments, the sled may be embodied as a compute sled, an accelerator sled, or a storage sled.
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公开(公告)号:US20180027313A1
公开(公告)日:2018-01-25
申请号:US15396035
申请日:2016-12-30
Applicant: Intel Corporation
Inventor: Matthew J. Adiletta , Aaron Gorius , Myles Wilde , Michael T. Crocker
CPC classification number: H04Q11/0005 , B25J15/0014 , B65G1/0492 , G02B6/3882 , G02B6/3893 , G02B6/3897 , G02B6/4292 , G02B6/4452 , G05D23/1921 , G05D23/2039 , G06F1/183 , G06F3/061 , G06F3/0611 , G06F3/0616 , G06F3/0619 , G06F3/0625 , G06F3/0631 , G06F3/0638 , G06F3/064 , G06F3/0647 , G06F3/0653 , G06F3/0658 , G06F3/0659 , G06F3/0664 , G06F3/0665 , G06F3/067 , G06F3/0673 , G06F3/0679 , G06F3/0683 , G06F3/0688 , G06F3/0689 , G06F8/65 , G06F9/4401 , G06F9/5016 , G06F9/5044 , G06F9/505 , G06F9/5072 , G06F9/5077 , G06F11/141 , G06F11/3414 , G06F12/0862 , G06F12/0893 , G06F12/10 , G06F12/109 , G06F12/1408 , G06F13/161 , G06F13/1668 , G06F13/1694 , G06F13/4022 , G06F13/4068 , G06F13/409 , G06F13/42 , G06F13/4282 , G06F15/8061 , G06F17/30949 , G06F2209/5019 , G06F2209/5022 , G06F2212/1008 , G06F2212/1024 , G06F2212/1041 , G06F2212/1044 , G06F2212/152 , G06F2212/202 , G06F2212/401 , G06F2212/402 , G06F2212/7207 , G06Q10/06 , G06Q10/06314 , G06Q10/087 , G06Q10/20 , G06Q50/04 , G07C5/008 , G08C17/02 , G08C2200/00 , G11C5/02 , G11C5/06 , G11C7/1072 , G11C11/56 , G11C14/0009 , H03M7/30 , H03M7/3084 , H03M7/3086 , H03M7/40 , H03M7/4031 , H03M7/4056 , H03M7/4081 , H03M7/6005 , H03M7/6023 , H04B10/25 , H04B10/2504 , H04L9/0643 , H04L9/14 , H04L9/3247 , H04L9/3263 , H04L12/2809 , H04L29/12009 , H04L41/024 , H04L41/046 , H04L41/0813 , H04L41/082 , H04L41/0896 , H04L41/12 , H04L41/145 , H04L41/147 , H04L41/5019 , H04L43/065 , H04L43/08 , H04L43/0817 , H04L43/0876 , H04L43/0894 , H04L43/16 , H04L45/02 , H04L45/52 , H04L47/24 , H04L47/765 , H04L47/782 , H04L47/805 , H04L47/82 , H04L47/823 , H04L49/15 , H04L49/25 , H04L49/357 , H04L49/45 , H04L49/555 , H04L67/02 , H04L67/10 , H04L67/1004 , H04L67/1008 , H04L67/1012 , H04L67/1014 , H04L67/1029 , H04L67/1034 , H04L67/1097 , H04L67/12 , H04L67/16 , H04L67/306 , H04L67/34 , H04L69/04 , H04L69/329 , H04Q1/04 , H04Q11/00 , H04Q11/0003 , H04Q11/0062 , H04Q11/0071 , H04Q2011/0037 , H04Q2011/0041 , H04Q2011/0052 , H04Q2011/0073 , H04Q2011/0079 , H04Q2011/0086 , H04Q2213/13523 , H04Q2213/13527 , H04W4/023 , H04W4/80 , H05K1/0203 , H05K1/181 , H05K5/0204 , H05K7/1418 , H05K7/1421 , H05K7/1422 , H05K7/1447 , H05K7/1461 , H05K7/1485 , H05K7/1487 , H05K7/1489 , H05K7/1491 , H05K7/1492 , H05K7/1498 , H05K7/2039 , H05K7/20709 , H05K7/20727 , H05K7/20736 , H05K7/20745 , H05K7/20836 , H05K13/0486 , H05K2201/066 , H05K2201/10121 , H05K2201/10159 , H05K2201/10189 , Y10S901/01
Abstract: Technologies for optical communication in a rack cluster in a data center are disclosed. In the illustrative embodiment, a network switch is connected to each of 1,024 sleds by an optical cable that enables communication at a rate of 200 gigabits per second. The optical cable has low loss, allowing for long cable lengths, which in turn allows for connecting to a large number of sleds. The optical cable also has a very high intrinsic bandwidth limit, allowing for the bandwidth to be upgraded without upgrading the optical infrastructure.
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公开(公告)号:US20180026851A1
公开(公告)日:2018-01-25
申请号:US15395995
申请日:2016-12-30
Applicant: Intel Corporation
Inventor: Matthew J. Adiletta , Aaron Gorius , Myles Wilde , Michael T. Crocker
CPC classification number: H04Q11/0005 , B25J15/0014 , B65G1/0492 , G02B6/3882 , G02B6/3893 , G02B6/3897 , G02B6/4292 , G02B6/4452 , G05D23/1921 , G05D23/2039 , G06F1/183 , G06F3/061 , G06F3/0611 , G06F3/0613 , G06F3/0616 , G06F3/0619 , G06F3/0625 , G06F3/0631 , G06F3/0638 , G06F3/064 , G06F3/0647 , G06F3/0653 , G06F3/0655 , G06F3/0658 , G06F3/0659 , G06F3/0664 , G06F3/0665 , G06F3/067 , G06F3/0673 , G06F3/0679 , G06F3/0683 , G06F3/0688 , G06F3/0689 , G06F8/65 , G06F9/30036 , G06F9/3887 , G06F9/4401 , G06F9/5016 , G06F9/5044 , G06F9/505 , G06F9/5072 , G06F9/5077 , G06F9/544 , G06F11/141 , G06F11/3414 , G06F12/0862 , G06F12/0893 , G06F12/10 , G06F12/109 , G06F12/1408 , G06F13/161 , G06F13/1668 , G06F13/1694 , G06F13/4022 , G06F13/4068 , G06F13/409 , G06F13/42 , G06F13/4282 , G06F15/8061 , G06F16/9014 , G06F2209/5019 , G06F2209/5022 , G06F2212/1008 , G06F2212/1024 , G06F2212/1041 , G06F2212/1044 , G06F2212/152 , G06F2212/202 , G06F2212/401 , G06F2212/402 , G06F2212/7207 , G06Q10/06 , G06Q10/06314 , G06Q10/087 , G06Q10/20 , G06Q50/04 , G07C5/008 , G08C17/02 , G08C2200/00 , G11C5/02 , G11C5/06 , G11C7/1072 , G11C11/56 , G11C14/0009 , H03M7/30 , H03M7/3084 , H03M7/3086 , H03M7/40 , H03M7/4031 , H03M7/4056 , H03M7/4081 , H03M7/6005 , H03M7/6023 , H04B10/25 , H04B10/2504 , H04L9/0643 , H04L9/14 , H04L9/3247 , H04L9/3263 , H04L12/2809 , H04L29/12009 , H04L41/024 , H04L41/046 , H04L41/0813 , H04L41/082 , H04L41/0896 , H04L41/12 , H04L41/145 , H04L41/147 , H04L41/5019 , H04L43/065 , H04L43/08 , H04L43/0817 , H04L43/0876 , H04L43/0894 , H04L43/16 , H04L45/02 , H04L45/52 , H04L47/24 , H04L47/38 , H04L47/765 , H04L47/782 , H04L47/805 , H04L47/82 , H04L47/823 , H04L49/00 , H04L49/15 , H04L49/25 , H04L49/357 , H04L49/45 , H04L49/555 , H04L67/02 , H04L67/10 , H04L67/1004 , H04L67/1008 , H04L67/1012 , H04L67/1014 , H04L67/1029 , H04L67/1034 , H04L67/1097 , H04L67/12 , H04L67/16 , H04L67/306 , H04L67/34 , H04L69/04 , H04L69/329 , H04Q1/04 , H04Q11/00 , H04Q11/0003 , H04Q11/0062 , H04Q11/0071 , H04Q2011/0037 , H04Q2011/0041 , H04Q2011/0052 , H04Q2011/0073 , H04Q2011/0079 , H04Q2011/0086 , H04Q2213/13523 , H04Q2213/13527 , H04W4/023 , H04W4/80 , H05K1/0203 , H05K1/181 , H05K5/0204 , H05K7/1418 , H05K7/1421 , H05K7/1422 , H05K7/1442 , H05K7/1447 , H05K7/1461 , H05K7/1485 , H05K7/1487 , H05K7/1489 , H05K7/1491 , H05K7/1492 , H05K7/1498 , H05K7/2039 , H05K7/20709 , H05K7/20727 , H05K7/20736 , H05K7/20745 , H05K7/20836 , H05K13/0486 , H05K2201/066 , H05K2201/10121 , H05K2201/10159 , H05K2201/10189 , Y02D10/14 , Y02D10/151 , Y02P90/30 , Y04S10/54 , Y10S901/01
Abstract: Technologies for connecting data cables in a data center are disclosed. In the illustrative embodiment, racks of the data center are grouped into different zones based on the distance from the racks in a given zone to a network switch. All of the racks in a given zone are connected to the network switch using data cables of the same length. In some embodiments, certain physical resources such as storage may be placed in racks that are in zones closer to the network switch and therefore use shorter data cables with lower latency. An orchestrator server may, in some embodiments, schedule workloads or create virtual servers based on the different zones and corresponding latency of different physical resources.
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公开(公告)号:US20160071558A1
公开(公告)日:2016-03-10
申请号:US14882867
申请日:2015-10-14
Applicant: Intel Corporation
Inventor: Gilbert Wolrich , Debra Bernstein , Daniel Cutter , Christopher Dolan , Matthew J. Adiletta
IPC: G11C7/10 , G06F15/173
CPC classification number: G06F13/20 , G06F3/0622 , G06F3/0661 , G06F3/0679 , G06F12/0223 , G06F12/0284 , G06F12/06 , G06F12/0806 , G06F12/10 , G06F12/109 , G06F13/28 , G06F13/4027 , G06F15/17318 , G06F15/76 , G06F2212/1041 , G06F2212/206 , G06F2212/251 , G11C7/1033 , G11C7/1072
Abstract: The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.
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公开(公告)号:US20160070664A1
公开(公告)日:2016-03-10
申请号:US14882897
申请日:2015-10-14
Applicant: Intel Corporation
Inventor: Gilbert Wolrich , Debra Bernstein , Daniel Cutter , Christopher Dolan , Matthew J. Adiletta
CPC classification number: G06F13/20 , G06F3/0622 , G06F3/0661 , G06F3/0679 , G06F12/0223 , G06F12/0284 , G06F12/06 , G06F12/0806 , G06F12/10 , G06F12/109 , G06F13/28 , G06F13/4027 , G06F15/17318 , G06F15/76 , G06F2212/1041 , G06F2212/206 , G06F2212/251 , G11C7/1033 , G11C7/1072
Abstract: The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.
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公开(公告)号:US20160034420A1
公开(公告)日:2016-02-04
申请号:US14882824
申请日:2015-10-14
Applicant: Intel Corporation
Inventor: Gilbert Wolrich , Debra Bernstein , Daniel Cutter , Christopher Dolan , Matthew J. Adiletta
IPC: G06F15/76
CPC classification number: G06F13/20 , G06F3/0622 , G06F3/0661 , G06F3/0679 , G06F12/0223 , G06F12/0284 , G06F12/06 , G06F12/0806 , G06F12/10 , G06F12/109 , G06F13/28 , G06F13/4027 , G06F15/17318 , G06F15/76 , G06F2212/1041 , G06F2212/206 , G06F2212/251 , G11C7/1033 , G11C7/1072
Abstract: The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.
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公开(公告)号:US11237840B2
公开(公告)日:2022-02-01
申请号:US16091201
申请日:2016-04-26
Applicant: Intel Corporation
Inventor: Matthew J. Adiletta , Myles Wilde , Michael F. Fallon , Amit Kumar , Chengda Yang , Aaron Gorius , William R. Wheeler
IPC: G06F9/00 , G06F9/4401 , G06F1/16 , G06F13/40 , G06K19/04
Abstract: All in one mobile computing devices and methods performed by the devices. The all in one mobile computing device includes a processor, memory, and software instructions configured to be executed on the processor to enable the mobile computing device to perform various operations. The all in one device may include various wired and wireless interfaces that enable it to communicate with a wide-range of devices, including smartphones, tablets, laptops, personal computers, smart TVs, and others. The all in one device is capable of being remotely accessed when linked in communication with a second device, and is enabled to aggregate data from various user devices and cloud-based services to create unified data resources. Data that is accessed by the device may be synched with a cloud-based storage service to enable a user to access data from across a range of devices via the all in one device. The all in one device has a form factor that is approximately the size of a credit card, yet is capable of running a full-fledged desktop operating system.
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公开(公告)号:US10910746B2
公开(公告)日:2021-02-02
申请号:US16208543
申请日:2018-12-03
Applicant: Intel Corporation
Inventor: Russell Aoki , Aaron Gorius , Michael T. Crocker , Matthew J. Adiletta
Abstract: Sleds for operation in racks of data centers are disclosed herein. A sled includes a circuit board substrate, one or more physical resources, and one or more memory devices. The circuit board substrate has a top side and a bottom side arranged opposite the top side. The one or more physical resources are coupled to the top side of the circuit board substrate. The one or more memory devices are coupled to the bottom side of the circuit board substrate. Additionally, the sled includes a connector to electrically couple the one or more physical resources to the one or more memory devices.
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