公开(公告)号：US20220238383A1

公开(公告)日：2022-07-28

申请号：US17720150

申请日：2022-04-13

Applicant: Intel Corporation

Inventor： Roman W. OLAC-VAW ,  Walid M. HAFEZ ,  Chia-Hong JAN ,  Pei-Chi LIU

IPC: H01L21/8234 ,  H01L27/12 ,  H01L21/84 ,  H01L29/78 ,  H01L21/28 ,  H01L23/528 ,  H01L27/088 ,  H01L29/49 ,  H01L21/8238

Abstract: Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.

公开(公告)号：US20250098275A1

公开(公告)日：2025-03-20

申请号：US18967144

申请日：2024-12-03

Applicant: Intel Corporation

Inventor： Roman W. OLAC-VAW ,  Walid M. HAFEZ ,  Chia-Hong JAN ,  Pei-Chi LIU

IPC: H01L21/8234 ,  H01L21/28 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/528 ,  H01L27/088 ,  H01L27/12 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

Abstract: Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.

公开(公告)号：US20210090956A1

公开(公告)日：2021-03-25

申请号：US17112959

申请日：2020-12-04

Applicant: Intel Corporation

Inventor： Roman W. OLAC-VAW ,  Walid M. HAFEZ ,  Chia-Hong JAN ,  Pei-Chi LIU

IPC: H01L21/8234 ,  H01L27/12 ,  H01L21/84 ,  H01L29/78 ,  H01L21/28 ,  H01L23/528 ,  H01L27/088 ,  H01L29/49 ,  H01L21/8238

Abstract: Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.

公开(公告)号：US20200273752A1

公开(公告)日：2020-08-27

申请号：US15930700

申请日：2020-05-13

Applicant: Intel Corporation

Inventor： Roman W. OLAC-VAW ,  Walid M. HAFEZ ,  Chia-Hong JAN ,  Pei-Chi LIU

IPC: H01L21/8234 ,  H01L27/12 ,  H01L21/84 ,  H01L21/28 ,  H01L23/528 ,  H01L27/088 ,  H01L29/49 ,  H01L21/8238

Abstract: Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.

公开(公告)号：US20170162503A1

公开(公告)日：2017-06-08

申请号：US15327338

申请日：2014-08-19

Applicant: INTEL CORPORATION

Inventor： Roman OLAC-VAW ,  Walid HAFEZ ,  Chia-Hong JAN ,  Hsu-Yu CHANG ,  Ting CHANG ,  Rahul RAMASWAMY ,  Pei-Chi LIU ,  Neville DIAS

IPC: H01L23/525 ,  H01L29/78 ,  H01L29/423 ,  H01L21/768

Abstract: A MOS antifuse with an accelerated dielectric breakdown induced by a void or seam formed in the electrode. In some embodiments, the programming voltage at which a MOS antifuse undergoes dielectric breakdown is reduced through intentional damage to at least part of the MOS antifuse dielectric. In some embodiments, damage may be introduced during an etchback of an electrode material which has a seam formed during backfilling of the electrode material into an opening having a threshold aspect ratio. In further embodiments, a MOS antifuse bit-cell includes a MOS transistor and a MOS antifuse. The MOS transistor has a gate electrode that maintains a predetermined voltage threshold swing, while the MOS antifuse has a gate electrode with a void accelerated dielectric breakdown.

公开(公告)号：US20240038592A1

公开(公告)日：2024-02-01

申请号：US18378983

申请日：2023-10-11

Applicant: Intel Corporation

Inventor： Roman W. OLAC-VAW ,  Walid M. HAFEZ ,  Chia-Hong JAN ,  Pei-Chi LIU

IPC: H01L21/8234 ,  H01L27/12 ,  H01L21/84 ,  H01L29/78 ,  H01L21/28 ,  H01L23/528 ,  H01L27/088 ,  H01L29/49 ,  H01L21/8238

CPC classification number: H01L21/82345 ,  H01L27/1211 ,  H01L21/845 ,  H01L29/7855 ,  H01L21/28088 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/5283 ,  H01L27/0886 ,  H01L29/4966 ,  H01L21/823821 ,  H01L21/823842 ,  H01L29/66545

Abstract: Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.

公开(公告)号：US20190157153A1

公开(公告)日：2019-05-23

申请号：US16253760

申请日：2019-01-22

Applicant: Intel Corporation

Inventor： Roman W. OLAC-VAW ,  Walid M. HAFEZ ,  Chia-Hong JAN ,  Pei-Chi LIU

IPC: H01L21/8234 ,  H01L21/84 ,  H01L21/28 ,  H01L27/088 ,  H01L29/49 ,  H01L27/12 ,  H01L23/528

Abstract: Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.