公开(公告)号：US20220238383A1

公开(公告)日：2022-07-28

申请号：US17720150

申请日：2022-04-13

Applicant: Intel Corporation

Inventor： Roman W. OLAC-VAW ,  Walid M. HAFEZ ,  Chia-Hong JAN ,  Pei-Chi LIU

IPC: H01L21/8234 ,  H01L27/12 ,  H01L21/84 ,  H01L29/78 ,  H01L21/28 ,  H01L23/528 ,  H01L27/088 ,  H01L29/49 ,  H01L21/8238

Abstract: Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.

公开(公告)号：US20220077145A1

公开(公告)日：2022-03-10

申请号：US17529029

申请日：2021-11-17

Applicant: Intel Corporation

Inventor： Walid M. HAFEZ ,  Sridhar GOVINDARAJU ,  Mark LIU ,  Szuya S. LIAO ,  Chia-Hong JAN ,  Nick LINDERT ,  Christopher KENYON ,  Sairam SUBRAMANIAN

IPC: H01L27/088 ,  H01L23/528 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8234

Abstract: Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, and methods of fabricating unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, are described. In an example, integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin has a cut along a length of the second semiconductor fin. A gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. The gate endcap isolation structure has a substantially uniform width along the lengths of the first and second semiconductor fins.

公开(公告)号：US20200251470A1

公开(公告)日：2020-08-06

申请号：US16846896

申请日：2020-04-13

Applicant: Intel Corporation

Inventor： Curtis TSAI ,  Chia-Hong JAN ,  Jeng-Ya David YEH ,  Joodong PARK ,  Walid M. HAFEZ

IPC: H01L27/092 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/49 ,  H01L27/088 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

Abstract: Two or more types of fin-based transistors having different gate structures and formed on a single integrated circuit are described. The gate structures for each type of transistor are distinguished at least by the thickness or composition of the gate dielectric layer(s) or the composition of the work function metal layer(s) in the gate electrode. Methods are also provided for fabricating an integrated circuit having at least two different types of fin-based transistors, where the transistor types are distinguished by the thickness and composition of the gate dielectric layer(s) and/or the thickness and composition of the work function metal in the gate electrode.

公开(公告)号：US20200066907A1

公开(公告)日：2020-02-27

申请号：US16317708

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Chia-Hong JAN ,  Walid M. HAFEZ ,  Hsu-Yu CHANG ,  Neville L. DIAS ,  Rahul RAMASWAMY ,  Roman W. OLAC-VAW ,  Chen-Guan LEE

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/786

Abstract: A transistor device including a transistor including a body disposed on a substrate, a gate stack contacting at least two adjacent sides of the body and a source and a drain on opposing sides of the gate stack and a channel defined in the body between the source and the drain, wherein a conductivity of the channel is similar to a conductivity of the source and the drain. An input/output (IO) circuit including a driver circuit coupled to the logic circuit, the driver circuit including at least one transistor device is described. A method including forming a channel of a transistor device on a substrate including an electrical conductivity; forming a source and a drain on opposite sides of the channel, wherein the source and the drain include the same electrical conductivity as the channel; and forming a gate stack on the channel.

公开(公告)号：US20190304971A1

公开(公告)日：2019-10-03

申请号：US15941647

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Walid M. HAFEZ ,  Sridhar GOVINDARAJU ,  Mark LIU ,  Szuya S. LIAO ,  Chia-Hong JAN ,  Nick LINDERT ,  Christopher KENYON ,  Sairam SUBRAMANIAN

IPC: H01L27/088 ,  H01L23/528 ,  H01L29/06

Abstract: Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, and methods of fabricating unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, are described. In an example, integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin has a cut along a length of the second semiconductor fin. A gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. The gate endcap isolation structure has a substantially uniform width along the lengths of the first and second semiconductor fins.

公开(公告)号：US20180108727A1

公开(公告)日：2018-04-19

申请号：US15667333

申请日：2017-08-02

Applicant: INTEL CORPORATION

Inventor： Chen-Guan LEE ,  Walid HAFEZ ,  Chia-Hong JAN

IPC: H01L49/02 ,  H01L27/06 ,  H01L23/66 ,  H01L21/8234

CPC classification number: H01L28/20 ,  H01L21/8234 ,  H01L23/66 ,  H01L27/0629 ,  H01L27/0738 ,  H01L28/24 ,  H01L29/785

Abstract: Integrated circuit structures including a pillar resistor disposed over a surface of a substrate, and fabrication techniques to form such a resistor in conjunction with fabrication of a transistor over the substrate. Following embodiments herein, a small resistor footprint may be achieved by orienting the resistive length orthogonally to the substrate surface. In embodiments, the vertical resistor pillar is disposed over a first end of a conductive trace, a first resistor contact is further disposed on the pillar, and a second resistor contact is disposed over a second end of a conductive trace to render the resistor footprint substantially independent of the resistance value.Formation of a resistor pillar may be integrated with a replacement gate transistor process by concurrently forming the resistor pillar and sacrificial gate out of a same material, such as polysilicon. Pillar resistor contacts may also be concurrently formed with one or more transistor contacts.

公开(公告)号：US20170133461A1

公开(公告)日：2017-05-11

申请号：US15409065

申请日：2017-01-18

Applicant: Intel Corporation

Inventor： Walid M. HAFEZ ,  Chia-Hong JAN

IPC: H01L29/06 ,  H01L27/098

CPC classification number: H01L29/0649 ,  H01L27/098 ,  H01L29/0657 ,  H01L29/404 ,  H01L29/66166 ,  H01L29/66803 ,  H01L29/66901 ,  H01L29/808 ,  H01L29/8605

Abstract: A dielectric and isolation lower fin material is described that is useful for fin-based electronics. In some examples, a dielectric layer is on first and second sidewalls of a lower fin. The dielectric layer has a first upper end portion laterally adjacent to the first sidewall of the lower fin and a second upper end portion laterally adjacent to the second sidewall of the lower fin. An isolation material is laterally adjacent to the dielectric layer directly on the first and second sidewalls of the lower fin and a gate electrode is over a top of and laterally adjacent to sidewalls of an upper fin. The gate electrode is over the first and second upper end portions of the dielectric layer and the isolation material.

公开(公告)号：US20170018658A1

公开(公告)日：2017-01-19

申请号：US15121879

申请日：2014-07-14

Applicant: Intel Corporation

Inventor： Walid M. HAFEZ ,  Chia-Hong JAN

IPC: H01L29/8605 ,  H01L29/66 ,  H01L29/808

CPC classification number: H01L29/0649 ,  H01L27/098 ,  H01L29/0657 ,  H01L29/404 ,  H01L29/66166 ,  H01L29/66803 ,  H01L29/66901 ,  H01L29/808 ,  H01L29/8605

Abstract: A solid source-diffused junction is described for fin-based electronics. In one example, a fin is formed on a substrate. A glass of a first dopant type is deposited over the substrate and over a lower portion of the fin. A glass of a second dopant type is deposited over the substrate and the fin. The glass is annealed to drive the dopants into the fin and the substrate. The glass is removed and a first and a second contact are formed over the fin without contacting the lower portion of the fin.

Abstract translation: 对于基于鳍的电子器件描述了固体源极扩散结。 在一个示例中，在基板上形成翅片。 第一掺杂剂类型的玻璃沉积在衬底上并且在鳍的下部上方。 在衬底和鳍上沉积一层第二掺杂剂类型。 将玻璃退火以将掺杂剂驱动到翅片和基底中。 去除玻璃并且在翅片之上形成第一和第二接触件，而不接触翅片的下部。

公开(公告)号：US20240113128A1

公开(公告)日：2024-04-04

申请号：US18538795

申请日：2023-12-13

Applicant: Intel Corporation

Inventor： Walid M. HAFEZ ,  Jeng-Ya D. YEH ,  Curtis TSAI ,  Joodong PARK ,  Chia-Hong JAN ,  Gopinath BHIMARASETTI

IPC: H01L27/12 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L27/1211 ,  H01L21/02164 ,  H01L21/0228 ,  H01L21/02532 ,  H01L21/02598 ,  H01L21/28158 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/845 ,  H01L29/42356 ,  H01L29/51 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6681

Abstract: High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. The second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers.

公开(公告)号：US20230299087A1

公开(公告)日：2023-09-21

申请号：US18140931

申请日：2023-04-28

Applicant: Intel Corporation

Inventor： Curtis TSAI ,  Chia-Hong JAN ,  Jeng-Ya David YEH ,  Joodong PARK ,  Walid M. HAFEZ

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/49 ,  H01L21/28 ,  H01L29/423

CPC classification number: H01L27/0922 ,  H01L29/66795 ,  H01L29/7855 ,  H01L29/66484 ,  H01L29/408 ,  H01L21/823431 ,  H01L27/0886 ,  H01L21/823462 ,  H01L29/4966 ,  H01L29/40114 ,  H01L21/823456 ,  H01L27/0924 ,  H01L29/42364 ,  H01L29/7831 ,  H01L29/517

Abstract: Two or more types of fin-based transistors having different gate structures and formed on a single integrated circuit are described. The gate structures for each type of transistor are distinguished at least by the thickness or composition of the gate dielectric layer(s) or the composition of the work function metal layer(s) in the gate electrode. Methods are also provided for fabricating an integrated circuit having at least two different types of fin-based transistors, where the transistor types are distinguished by the thickness and composition of the gate dielectric layer(s) and/or the thickness and composition of the work function metal in the gate electrode.