公开(公告)号：US20210280683A1

公开(公告)日：2021-09-09

申请号：US16810156

申请日：2020-03-05

Applicant: Intel Corporation

Inventor： Tanuj TRIVEDI ,  Rahul RAMASWAMY ,  Jeong Dong KIM ,  Babak FALLAHAZAD ,  Hsu-Yu CHANG ,  Ting CHANG ,  Nidhi NIDHI ,  Walid M. HAFEZ

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/165 ,  H01L29/10 ,  H01L21/02

Abstract: Gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires above a substrate. A dielectric cap is over the first vertical arrangement of nanowires. A second vertical arrangement of nanowires is above the substrate. Individual ones of the second vertical arrangement of nanowires are laterally staggered with individual ones of the first vertical arrangement of nanowires and the dielectric cap.

公开(公告)号：US20210399002A1

公开(公告)日：2021-12-23

申请号：US16910020

申请日：2020-06-23

Applicant: Intel Corporation

Inventor： Tanuj TRIVEDI ,  Walid M. HAFEZ ,  Rohan BAMBERY ,  Daniel B. O'Brien ,  Christopher Alan NOLPH ,  Rahul RAMASWAMY ,  Ting CHANG

IPC: H01L27/11568 ,  H01L49/02 ,  H01L29/78 ,  H01L29/792 ,  H01L21/28 ,  H01L29/66

Abstract: Embodiments disclosed herein include a semiconductor device and methods of forming such a device. In an embodiment, the semiconductor device comprises a substrate and a transistor on the substrate. In an embodiment, the transistor comprises a first gate electrode, where the first gate electrode is part of a first array of gate electrodes with a first pitch. In an embodiment, the first gate electrode has a first average grain size. In an embodiment, the semiconductor device further comprises a component cell on the substrate. In an embodiment, the component cell comprises a second gate electrode, where the second gate electrode is part of a second array of gate electrodes with a second pitch that is larger than the first pitch. In an embodiment, the second gate electrode has a second average grain size that is larger than the first average grain size.

公开(公告)号：US20210183857A1

公开(公告)日：2021-06-17

申请号：US16713703

申请日：2019-12-13

Applicant: Intel Corporation

Inventor： Walid M. HAFEZ ,  Rahul RAMASWAMY ,  Tanuj TRIVEDI ,  Jeong Dong KIM ,  Ting CHANG ,  Babak FALLAHAZAD ,  Hsu-Yu CHANG ,  Nidhi NIDHI

IPC: H01L27/092 ,  H01L29/786 ,  H01L29/423 ,  H01L29/51 ,  H01L21/02

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such semiconductor devices. In an embodiment, the semiconductor device comprises a substrate, and a first transistor over the substrate. In an embodiment, the first transistor comprises a first semiconductor channel above the substrate, a first gate dielectric surrounding the first semiconductor channel, and a first gate electrode over the first gate dielectric. In an embodiment, the semiconductor device further comprises a second transistor over the substrate. In an embodiment, the second transistor comprises a second semiconductor channel above the substrate, a second gate dielectric surrounding the second semiconductor channel, where the second gate dielectric is different than the first gate dielectric, and a second gate electrode over the second gate dielectric, where the first gate electrode and the second gate electrode comprise the same material.

公开(公告)号：US20230420501A1

公开(公告)日：2023-12-28

申请号：US18244741

申请日：2023-09-11

Applicant: Intel Corporation

Inventor： Rahul RAMASWAMY ,  Walid M. HAFEZ ,  Tanuj TRIVEDI ,  Jeong Dong KIM ,  Ting CHANG ,  Babak FALLAHAZAD ,  Hsu-Yu CHANG ,  Nidhi NIDHI

IPC: H01L29/06 ,  H01L29/78 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/423

CPC classification number: H01L29/0669 ,  H01L29/785 ,  H01L27/0924 ,  H01L21/823821 ,  H01L21/823814 ,  H01L29/42392 ,  B82Y40/00

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a substrate, and a first transistor of a first conductivity type over the substrate. In an embodiment, the first transistor comprises a first semiconductor channel, and a first gate electrode around the first semiconductor channel. In an embodiment, the semiconductor device further comprises a second transistor of a second conductivity type above the first transistor. The second transistor comprises a second semiconductor channel, and a second gate electrode around the second semiconductor channel. In an embodiment, the second gate electrode and the first gate electrode comprise different materials.

公开(公告)号：US20210184001A1

公开(公告)日：2021-06-17

申请号：US16713684

申请日：2019-12-13

Applicant: Intel Corporation

Inventor： Tanuj TRIVEDI ,  Rahul RAMASWAMY ,  Jeong Dong KIM ,  Ting CHANG ,  Walid M. HAFEZ ,  Babak FALLAHAZAD ,  Hsu-Yu CHANG ,  Nidhi NIDHI

IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/78 ,  H01L27/088 ,  H01L29/66

Abstract: Embodiments disclosed herein include nanowire and nanoribbon devices with non-uniform dielectric thicknesses. In an embodiment, the semiconductor device comprises a substrate and a plurality of first semiconductor layers in a vertical stack over the substrate. The first semiconductor layers may have a first spacing. In an embodiment, a first dielectric surrounds each of the first semiconductor layers, and the first dielectric has a first thickness. The semiconductor device may further comprise a plurality of second semiconductor layers in a vertical stack over the substrate, where the second semiconductor layers have a second spacing that is greater than the first spacing. In an embodiment a second dielectric surrounds each of the second semiconductor layers, and the second dielectric has a second thickness that is greater than the first thickness.

公开(公告)号：US20210257453A1

公开(公告)日：2021-08-19

申请号：US17308900

申请日：2021-05-05

Applicant: Intel Corporation

Inventor： Tanuj TRIVEDI ,  Jeong Dong KIM ,  Walid M. HAFEZ ,  Hsu-Yu CHANG ,  Rahul RAMASWAMY ,  Ting CHANG ,  Babak FALLAHAZAD

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/10 ,  H01L29/08 ,  H01L27/088

Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate, the first vertical arrangement of nanowires having a greater number of active nanowires than the second vertical arrangement of nanowires, and the first and second vertical arrangements of nanowires having co-planar uppermost nanowires. The integrated circuit structure also includes a first vertical arrangement of nanoribbons and a second vertical arrangement of nanoribbons above the substrate, the first vertical arrangement of nanoribbons having a greater number of active nanoribbons than the second vertical arrangement of nanoribbons, and the first and second vertical arrangements of nanoribbons having co-planar uppermost nanoribbons.

公开(公告)号：US20210257452A1

公开(公告)日：2021-08-19

申请号：US16795081

申请日：2020-02-19

Applicant: Intel Corporation

Inventor： Tanuj TRIVEDI ,  Jeong Dong KIM ,  Walid M. HAFEZ ,  Hsu-Yu CHANG ,  Rahul RAMASWAMY ,  Ting CHANG ,  Babak FALLAHAZAD

IPC: H01L29/06 ,  H01L29/10 ,  H01L27/088 ,  H01L29/423 ,  H01L29/08 ,  H01L21/8234

Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate, the first vertical arrangement of nanowires having a greater number of active nanowires than the second vertical arrangement of nanowires, and the first and second vertical arrangements of nanowires having co-planar uppermost nanowires. The integrated circuit structure also includes a first vertical arrangement of nanoribbons and a second vertical arrangement of nanoribbons above the substrate, the first vertical arrangement of nanoribbons having a greater number of active nanoribbons than the second vertical arrangement of nanoribbons, and the first and second vertical arrangements of nanoribbons having co-planar uppermost nanoribbons.

公开(公告)号：US20210184051A1

公开(公告)日：2021-06-17

申请号：US16713619

申请日：2019-12-13

Applicant: Intel Corporation

Inventor： Tanuj TRIVEDI ,  Rahul RAMASWAMY ,  Jeong Dong KIM ,  Ting CHANG ,  Walid M. HAFEZ ,  Babak FALLAHAZAD ,  Hsu-Yu CHANG ,  Nidhi NIDHI

IPC: H01L29/786 ,  H01L27/088 ,  H01L29/423 ,  H01L21/8234

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a substrate, a first transistor over the substrate, where the first transistor comprises a vertical stack of first semiconductor channels, and a first gate dielectric surrounding each of the first semiconductor channels. The first gate dielectric has a first thickness. In an embodiment, the semiconductor device further comprises a second transistor over the substrate, where the second transistor comprises a second semiconductor channel. The second semiconductor channel comprises pair of sidewalls and a top surface. In an embodiment, a second gate dielectric is over the pair of sidewalls and the top surface of the fin, where the second gate dielectric has a second thickness that is greater than the first thickness.

公开(公告)号：US20210184045A1

公开(公告)日：2021-06-17

申请号：US16713600

申请日：2019-12-13

Applicant: Intel Corporation

Inventor： Rahul RAMASWAMY ,  Walid M. HAFEZ ,  Nidhi NIDHI ,  Ting CHANG ,  Hsu-Yu CHANG ,  Tanuj TRIVEDI ,  Jeong Dong KIM ,  Babak FALLAHAZAD

IPC: H01L29/786 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L21/8238

Abstract: Embodiments disclosed herein include nanoribbon and nanowire semiconductor devices. In an embodiment, the semiconductor device comprises a nanowire disposed above a substrate. In an embodiment, the nanowire has a first dopant concentration, and the nanowire comprises a pair of tip regions on opposite ends of the nanowire. In an embodiment, the tip regions comprise a second dopant concentration that is greater than the first dopant concentration. In an embodiment, the semiconductor device further comprises a gate structure over the nanowire. In an embodiment, the gate structure is wrapped around the nanowire, and the gate structure defines a channel region of the device. In an embodiment, a pair of source/drain regions are on opposite sides of the gate structure, and both source/drain regions contact the nanowire.

公开(公告)号：US20170162503A1

公开(公告)日：2017-06-08

申请号：US15327338

申请日：2014-08-19

Applicant: INTEL CORPORATION

Inventor： Roman OLAC-VAW ,  Walid HAFEZ ,  Chia-Hong JAN ,  Hsu-Yu CHANG ,  Ting CHANG ,  Rahul RAMASWAMY ,  Pei-Chi LIU ,  Neville DIAS

IPC: H01L23/525 ,  H01L29/78 ,  H01L29/423 ,  H01L21/768

Abstract: A MOS antifuse with an accelerated dielectric breakdown induced by a void or seam formed in the electrode. In some embodiments, the programming voltage at which a MOS antifuse undergoes dielectric breakdown is reduced through intentional damage to at least part of the MOS antifuse dielectric. In some embodiments, damage may be introduced during an etchback of an electrode material which has a seam formed during backfilling of the electrode material into an opening having a threshold aspect ratio. In further embodiments, a MOS antifuse bit-cell includes a MOS transistor and a MOS antifuse. The MOS transistor has a gate electrode that maintains a predetermined voltage threshold swing, while the MOS antifuse has a gate electrode with a void accelerated dielectric breakdown.