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公开(公告)号：US20200007116A1
公开(公告)日：2020-01-02
申请号：US16025148
申请日：2018-07-02
Applicant: Intel Corporation
Inventor： Abhishek Agrawal , Stefano Pellerano , Yanjie Wang , Peter Sagazio
Abstract: In a phase modulation method enable signals may be sequentially generating based on a clock signal to generate a sequence of enable signals, and a signal is delayed by delay values generated from delay cells based on the sequence of enable signals and digital bit values. A phase modulator may include a first delay circuit configured to: delay a clock signal based on a first delay value to generate a first delayed clock signal, and delay a carrier signal based on the first delayed clock signal to generate a first delayed carrier signal; and a second delay circuit configured to: delay the first delayed clock signal based on a second delay value to generate a second delayed clock signal, and delay the first delayed carrier signal based on the second delayed clock signal to generate a second delayed carrier signal.
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2.发明授权公开(公告)号：US12212510B2
公开(公告)日：2025-01-28
申请号：US17124536
申请日：2020-12-17
Applicant: Intel Corporation
Inventor： Peter Sagazio , Chun C. Lee , Stefano Pellerano , Christopher D. Hull
Abstract: Various aspects of this disclosure provide a receiver. The receiver may include a down-converter configured to down-convert a received communication signal at a predefined carrier frequency, with a reference signal received from a reference signal generator, and a processor configured to perform a signal quality detection to identify a signal quality metric of the received communication signal at the predefined carrier frequency, and to provide a frequency adjusting signal to the reference signal generator to change the frequency of the reference signal based on the performed signal quality detection to identify the signal quality metric of the received communication signal at the predefined carrier frequency.
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公开(公告)号：US10594309B2
公开(公告)日：2020-03-17
申请号：US16025148
申请日：2018-07-02
Applicant: Intel Corporation
Inventor： Abhishek Agrawal , Stefano Pellerano , Yanjie Wang , Peter Sagazio
Abstract: In a phase modulation method enable signals may be sequentially generating based on a clock signal to generate a sequence of enable signals, and a signal is delayed by delay values generated from delay cells based on the sequence of enable signals and digital bit values. A phase modulator may include a first delay circuit configured to: delay a clock signal based on a first delay value to generate a first delayed clock signal, and delay a carrier signal based on the first delayed clock signal to generate a first delayed carrier signal; and a second delay circuit configured to: delay the first delayed clock signal based on a second delay value to generate a second delayed clock signal, and delay the first delayed carrier signal based on the second delayed clock signal to generate a second delayed carrier signal.
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Patent Agency Ranking
公开(公告)号：US12212351B2
公开(公告)日：2025-01-28
申请号：US17131872
申请日：2020-12-23
Applicant: Intel Corporation
Inventor： Abhishek Agrawal , Ritesh A. Bhat , Steven Callender , Brent R. Carlton , Christopher D. Hull , Stefano Pellerano , Mustafijur Rahman , Peter Sagazio , Woorim Shin
IPC: H04B1/04
Abstract: Various aspects provide a transceiver and a communication device including the transceiver. In an example, the transceiver includes an amplifier circuit including an amplifier stage with an adjustable degeneration component, the amplifier stage configured to amplify a received input signal with an adjustable gain, an adjustable feedback component coupled to the amplifier stage; and a controller coupled to the amplifier stage and to the adjustable feedback component and configured to adjust the adjustable feedback component based on an adjustment of the adjustable degeneration component.
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公开(公告)号：US11990932B2
公开(公告)日：2024-05-21
申请号：US17132893
申请日：2020-12-23
Applicant: Intel Corporation
Inventor： Mohamed A. Abdelmoneum , Nasser Kurd , Thripthi Hegde , Narayan Srinivasa , Peter Sagazio
IPC: H04B1/692 , H04B1/7136 , H04B1/7143 , H04B1/7156 , H04L9/08
CPC classification number: H04B1/7156 , H04B1/7136 , H04B1/7143 , H04L9/0869
Abstract: A clock buffer or driver is gated pending reception of verifiable crypto keys. These clock buffer or divers remain gated, thus disabling a processor from any meaningful function, till crypto keys are decoded, verified, and applied to the clock buffer or driver. A low frequency pseudorandom frequency hopping time sequence is generated and used for randomizing spread-spectrum to modulate a reference clock (or output clock) of a frequency synthesizer. This hopping time sequence holds the key to unlocking the crypto keys. The PWM modulated crypto keys are carried by the hopping time sequence. To decode the PWM modulated crypto keys, the hopping time sequence is used. The reference clock which is modulated with crypto keys in the spread-spectrum is sent to a decoder (in a processor) along with the hopping time sequence. The crypto keys are decoded and then used to un-gate the clock buffer.
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公开(公告)号：US20220200655A1
公开(公告)日：2022-06-23
申请号：US17132893
申请日：2020-12-23
Applicant: Intel Corporation
Inventor： Mohamed A. Abdelmoneum , Nasser Kurd , Thripthi Hegde , Narayan Srinivasa , Peter Sagazio
IPC: H04B1/7156 , H04B1/7136 , H04B1/7143 , H04L9/08
Abstract: A clock buffer or driver is gated pending reception of verifiable crypto keys. These clock buffer or divers remain gated, thus disabling a processor from any meaningful function, till crypto keys are decoded, verified, and applied to the clock buffer or driver. A low frequency pseudorandom frequency hopping time sequence is generated and used for randomizing spread-spectrum to modulate a reference clock (or output clock) of a frequency synthesizer. This hopping time sequence holds the key to unlocking the crypto keys. The PWM modulated crypto keys are carried by the hopping time sequence. To decode the PWM modulated crypto keys, the hopping time sequence is used. The reference clock which is modulated with crypto keys in the spread-spectrum is sent to a decoder (in a processor) along with the hopping time sequence. The crypto keys are decoded and then used to un-gate the clock buffer.
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公开(公告)号：US20250004222A1
公开(公告)日：2025-01-02
申请号：US18345044
申请日：2023-06-30
Applicant: Intel Corporation
Inventor： Debabani Choudhury , Huimin Chen , Eric Gantner , Stephen Hall , Cooper Levy , Shawn Mceuen , Luis Paniagua Acuna , Peter Sagazio , Harry Skinner , Kerry Stevens , Ana Yepes
Abstract: A rotatable circular waveguide structure is described that may comprise circular waveguide sections configured to propagate electromagnetic radiation. The circular waveguide sections may enable data signals to be transmitted between portions of an electronic device, such as a chassis and display portion, which may be rotatable with respect to one another. The rotatable circular waveguide structure may comprise one or more circular waveguide sections that are routed through a hinge of the electronic device, as well as one or more rotatable junctions. The rotatable junctions enable a rotation of circular waveguide sections with respect to one another as the coupled portions of the electronic device are also rotated. The rotatable circular waveguide structure may replace the use of data cables that are conventionally used to carry data signals between portions of an electronic device.
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公开(公告)号：US20210075456A1
公开(公告)日：2021-03-11
申请号：US16958813
申请日：2018-01-02
Applicant: INTEL CORPORATION
Inventor： Oner Orhan , Hosein Nikopour , Peter Sagazio , Farhana Sheikh , Junyoung Nam , Shilpa Talwar
IPC: H04B1/16
Abstract: A receiver circuit associated with a communication device is disclosed. The receiver circuit comprises a digital data compression circuit configured to receive a plurality of digital receive signals derived from a plurality of analog receive signals respectively associated with the receiver circuit. The digital data compression circuit is further configured to compress the plurality of digital receive signals to form one or more compressed digital data signals based thereon, to be provided to an input output (I/O) interface associated therewith. In some embodiments, a compressed digital signal dimension associated with the one or more compressed digital data signals is less than a digital signal dimension associated with the plurality of digital receive signals.
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