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公开(公告)号：US20200004990A1
公开(公告)日：2020-01-02
申请号：US16020918
申请日：2018-06-27
Applicant: Intel Corporation
Inventor： Nasser Kurd , Praveen Mosalikanti , Thripthi Hegde , Mark Neidengard , Vaughn Grossnickle , Qi S. Wang , Kandadai Ramesh
Abstract: An apparatus is provided for autonomous security and functional safety (FUSA) of clock and voltages. The apparatus may include: a multiplexer having a first input communicatively coupled to a pin to receive a first clock external to a die, and a second input coupled to an output of a divider; an oscillator to provide a second clock; and a counter coupled to an output of the multiplexer and the oscillator, wherein the counter is to operate with the second clock and is to determine a frequency of the first clock. The apparatus may further include a voltage monitor circuitry for monitoring voltage(s) for FUSA, a reference generator for FUSA, a duty cycle monitor for FUSA, a frequency degradation monitor for FUSA, and a phase error degradation monitor for FUSA.
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公开(公告)号：US20220200655A1
公开(公告)日：2022-06-23
申请号：US17132893
申请日：2020-12-23
Applicant: Intel Corporation
Inventor： Mohamed A. Abdelmoneum , Nasser Kurd , Thripthi Hegde , Narayan Srinivasa , Peter Sagazio
IPC: H04B1/7156 , H04B1/7136 , H04B1/7143 , H04L9/08
Abstract: A clock buffer or driver is gated pending reception of verifiable crypto keys. These clock buffer or divers remain gated, thus disabling a processor from any meaningful function, till crypto keys are decoded, verified, and applied to the clock buffer or driver. A low frequency pseudorandom frequency hopping time sequence is generated and used for randomizing spread-spectrum to modulate a reference clock (or output clock) of a frequency synthesizer. This hopping time sequence holds the key to unlocking the crypto keys. The PWM modulated crypto keys are carried by the hopping time sequence. To decode the PWM modulated crypto keys, the hopping time sequence is used. The reference clock which is modulated with crypto keys in the spread-spectrum is sent to a decoder (in a processor) along with the hopping time sequence. The crypto keys are decoded and then used to un-gate the clock buffer.
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公开(公告)号：US10824764B2
公开(公告)日：2020-11-03
申请号：US16020918
申请日：2018-06-27
Applicant: Intel Corporation
Inventor： Nasser Kurd , Praveen Mosalikanti , Thripthi Hegde , Mark Neidengard , Vaughn Grossnickle , Qi S. Wang , Kandadai Ramesh
Abstract: An apparatus is provided for autonomous security and functional safety (FUSA) of clock and voltages. The apparatus may include: a multiplexer having a first input communicatively coupled to a pin to receive a first clock external to a die, and a second input coupled to an output of a divider; an oscillator to provide a second clock; and a counter coupled to an output of the multiplexer and the oscillator, wherein the counter is to operate with the second clock and is to determine a frequency of the first clock. The apparatus may further include a voltage monitor circuitry for monitoring voltage(s) for FUSA, a reference generator for FUSA, a duty cycle monitor for FUSA, a frequency degradation monitor for FUSA, and a phase error degradation monitor for FUSA.
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Patent Agency Ranking
公开(公告)号：US11990932B2
公开(公告)日：2024-05-21
申请号：US17132893
申请日：2020-12-23
Applicant: Intel Corporation
Inventor： Mohamed A. Abdelmoneum , Nasser Kurd , Thripthi Hegde , Narayan Srinivasa , Peter Sagazio
IPC: H04B1/692 , H04B1/7136 , H04B1/7143 , H04B1/7156 , H04L9/08
CPC classification number: H04B1/7156 , H04B1/7136 , H04B1/7143 , H04L9/0869
Abstract: A clock buffer or driver is gated pending reception of verifiable crypto keys. These clock buffer or divers remain gated, thus disabling a processor from any meaningful function, till crypto keys are decoded, verified, and applied to the clock buffer or driver. A low frequency pseudorandom frequency hopping time sequence is generated and used for randomizing spread-spectrum to modulate a reference clock (or output clock) of a frequency synthesizer. This hopping time sequence holds the key to unlocking the crypto keys. The PWM modulated crypto keys are carried by the hopping time sequence. To decode the PWM modulated crypto keys, the hopping time sequence is used. The reference clock which is modulated with crypto keys in the spread-spectrum is sent to a decoder (in a processor) along with the hopping time sequence. The crypto keys are decoded and then used to un-gate the clock buffer.
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公开(公告)号：US11442492B2
公开(公告)日：2022-09-13
申请号：US16292204
申请日：2019-03-04
Applicant: Intel Corporation
Inventor： Mohamed A. Abdelmoneum , Nasser A. Kurd , Thripthi Hegde
Abstract: An apparatus and method to protect unauthorized change to a reference clock for a processor. The apparatus comprises: a first oscillator to generate a first clock; a second oscillator to generate a second clock; a third oscillator to generate a third clock; a first counter to count frequency of the first clock with respect to a fourth clock; a second counter to count frequency of the second clock with respect to the fourth clock; a third counter to count frequency of the third clock with respect to the fourth clock; and a circuitry to compare frequencies of the first, second, and third clocks with one another. The oscillators can be embedded in an interposer or package. These oscillators include one or more of: LC oscillator, micro electro-mechanical system (MEMs) based resonator, or ring oscillator.
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公开(公告)号：US11461504B2
公开(公告)日：2022-10-04
申请号：US17087414
申请日：2020-11-02
Applicant: Intel Corporation
Inventor： Nasser Kurd , Praveen Mosalikanti , Thripthi Hegde , Mark Neidengard , Vaughn Grossnickle , Qi S. Wang , Kandadai Ramesh
Abstract: An apparatus is provided for autonomous security and functional safety (FUSA) of clock and voltages. The apparatus may include: a multiplexer having a first input communicatively coupled to a pin to receive a first clock external to a die, and a second input coupled to an output of a divider; an oscillator to provide a second clock; and a counter coupled to an output of the multiplexer and the oscillator, wherein the counter is to operate with the second clock and is to determine a frequency of the first clock. The apparatus may further include a voltage monitor circuitry for monitoring voltage(s) for FUSA, a reference generator for FUSA, a duty cycle monitor for FUSA, a frequency degradation monitor for FUSA, and a phase error degradation monitor for FUSA.
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公开(公告)号：US20210049307A1
公开(公告)日：2021-02-18
申请号：US17087414
申请日：2020-11-02
Applicant: Intel Corporation
Inventor： Nasser Kurd , Praveen Mosalikanti , Thripthi Hegde , Mark Neidengard , Vaughn Grossnickle , Qi S. Wang , Kandadai Ramesh
Abstract: An apparatus is provided for autonomous security and functional safety (FUSA) of clock and voltages. The apparatus may include: a multiplexer having a first input communicatively coupled to a pin to receive a first clock external to a die, and a second input coupled to an output of a divider; an oscillator to provide a second clock; and a counter coupled to an output of the multiplexer and the oscillator, wherein the counter is to operate with the second clock and is to determine a frequency of the first clock. The apparatus may further include a voltage monitor circuitry for monitoring voltage(s) for FUSA, a reference generator for FUSA, a duty cycle monitor for FUSA, a frequency degradation monitor for FUSA, and a phase error degradation monitor for FUSA.
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公开(公告)号：US20200285267A1
公开(公告)日：2020-09-10
申请号：US16292204
申请日：2019-03-04
Applicant: Intel Corporation
Inventor： Mohamed A. Abdelmoneum , Nasser A. Kurd , Thripthi Hegde
Abstract: An apparatus and method to protect unauthorized change to a reference clock for a processor. The apparatus comprises: a first oscillator to generate a first clock; a second oscillator to generate a second clock; a third oscillator to generate a third clock; a first counter to count frequency of the first clock with respect to a fourth clock; a second counter to count frequency of the second clock with respect to the fourth clock; a third counter to count frequency of the third clock with respect to the fourth clock; and a circuitry to compare frequencies of the first, second, and third clocks with one another. The oscillators can be embedded in an interposer or package. These oscillators include one or more of: LC oscillator, micro electro-mechanical system (MEMs) based resonator, or ring oscillator.
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