-
公开(公告)号：US10002654B2
公开(公告)日：2018-06-19
申请号：US14752464
申请日：2015-06-26
Applicant: Intel Corporation
Inventor： Jaydeep P Kulkarni , Pramod Kolar , Ankit Sharma , Subho Chatterjee , Karthik Subramanian , Farhana Sheikh , Wei-Hsiang Ma
IPC: G11C8/08 , G11C7/18 , G11C11/413 , G11C11/418 , G11C11/419 , G11C5/14
CPC classification number: G11C8/08 , G11C5/145 , G11C7/18 , G11C11/413 , G11C11/418 , G11C11/419
Abstract: In some embodiments, disclosed is a wordline boosting technique using a self-timed capacitive charge boosting approach.
-
公开(公告)号：US09893746B2
公开(公告)日：2018-02-13
申请号：US14749766
申请日：2015-06-25
Applicant: Intel Corporation
Inventor： Farhana Sheikh , Ching-En Lee , Shu-Ping Yeh , Feng Xue , Anuja Surendra Vaidya
CPC classification number: H04B1/0475 , H04B1/12 , H04B1/525 , H04L5/14
Abstract: A polynomial kernel generator is configured to mitigate nonlinearity in a receiver path from a transmitter path comprising a nonlinear component in a communication device or system. The polynomial kernel generator operates to generate polynomial kernels that can be utilized to model the nonlinearity as a function of a piecewise polynomial approximation applied to a nonlinear function of the nonlinearity. The polynomial kernel generator generates kernels in a multiplier less architecture with polynomial computations in a log domain using a fixed number of adders.
-
公开(公告)号：US09698838B1
公开(公告)日：2017-07-04
申请号：US14998107
申请日：2015-12-23
Applicant: Intel Corporation
Inventor： Shreyas Sen , Ritesh Bhat , Yanjie Wang , Stefano Pellerano , Christopher Hull , Farhana Sheikh
CPC classification number: H04B1/1027 , H04B1/16 , H04L27/14 , H04W52/0209 , H04W52/0229 , H04W52/0238 , H04W52/0245 , H04W88/06 , Y02D70/1262 , Y02D70/142 , Y02D70/144
Abstract: A receiver system includes a blocker detector circuit configured to receive a radio frequency (RF) input signal and detect an existence of a blocker therein, and further configured to output a blocker detection signal indicative of the existence of the blocker. The receiver system further includes a configurable receiver circuit configured to receive the RF input signal and the blocker detection signal, and selectively configure the configurable receiver circuit between a first mode wherein the configurable receiver circuit exhibits first linearity characteristics, and a second mode wherein the configurable receiver circuit exhibits second, different linearity characteristics based on the blocker detection signal.
-
4.发明授权Digital intensive hybrid ADC/filter for LNA-free adaptive radio front-ends 有权数字强度混合ADC /滤波器，用于无LNA自适应无线电前端公开(公告)号：US09584164B1
公开(公告)日：2017-02-28
申请号：US15049616
申请日：2016-02-22
Applicant: Intel Corporation
Inventor： Farhana Sheikh , Amy L. Whitcombe , Erkan Alpman , Yanjie Wang , Shreyas Sen
CPC classification number: H04B1/0042 , H04B1/10 , H04L27/0002
Abstract: A mixer-first receiver operates to generate filtering and analog-to-digital conversion concurrently and adaptively, while removing an LNA before a mixer to enable integration with digital baseband circuits. A plurality of switching capacitor arrays are integrated with a hybrid analog-to-digital filtering component. Switching capacitor arrays of the plurality of switching capacitor arrays can be selectively modified to perform both the filtering operation and the conversion operation together. The same switch capacitors of a switching capacitor array can be utilized in one phase of a clock cycle for the filtering and in another phase of the clock cycle for the conversion.
Abstract translation: 混频器第一接收机用于同时和自适应地产生滤波和模数转换，同时在混频器之前去除LNA以实现与数字基带电路的集成。 多个开关电容器阵列与混合模数转换组件集成。 可以选择性地修改多个开关电容器阵列的开关电容器阵列以一起执行滤波操作和转换操作。 开关电容器阵列的相同开关电容器可以在用于滤波的时钟周期的一个阶段中用于转换的时钟周期的另一个阶段。
-
公开(公告)号：US20180287675A1
公开(公告)日：2018-10-04
申请号：US15763860
申请日：2015-10-30
Applicant: Intel Corporation
IPC: H04B7/0456
Abstract: An orthogonalization matrix calculation circuit may include a scaling coefficient calculation circuit configured to calculate a scaling coefficient for each of a plurality of candidate update operations for the orthogonalization matrix, wherein each of the plurality of candidate update operations comprises combining linearly at least one of a first column or a second column of the orthogonalization matrix previously utilized to update the orthogonalization matrix, an update operation selection circuit configured to select an optimum candidate update operation from the plurality of candidate update operations, and a matrix update circuit configured to update the orthogonalization matrix according to the scaling coefficient of the optimum candidate update operation.
-
Patent Agency Ranking
公开(公告)号：US09843352B2
公开(公告)日：2017-12-12
申请号：US14379869
申请日：2013-12-26
Applicant: Intel Corporation
Inventor： Hossein Alavi , Farhana Sheikh , Markus Dominik Mueck , Vladimir Ivanov
CPC classification number: H04B1/3838 , H04B15/02 , H04B17/102 , H04W52/44 , H04W52/50
Abstract: The disclosure generally relates to a method, apparatus and system for identifying non-compliant radio emissions and for enforcing compliance. In one embodiment, the disclosure relates to a dynamic radiation control of a radio by measuring a signal attribute for an outbound signal having a protocol; comparing the signal attribute with a predefined mask, the predefined mask governed by at least one of a radio location or a signal protocol; and determining whether to transmit the outbound signal.
-
公开(公告)号：US20170187405A1
公开(公告)日：2017-06-29
申请号：US14998107
申请日：2015-12-23
Applicant: Intel Corporation
Inventor： Shreyas Sen , Ritesh Bhat , Yanjie Wang , Stefano Pellerano , Christopher Hull , Farhana Sheikh
CPC classification number: H04B1/1027 , H04B1/16 , H04L27/14 , H04W52/0209 , H04W52/0229 , H04W52/0238 , H04W52/0245 , H04W88/06 , Y02D70/1262 , Y02D70/142 , Y02D70/144
Abstract: A receiver system includes a blocker detector circuit configured to receive a radio frequency (RF) input signal and detect an existence of a blocker therein, and further configured to output a blocker detection signal indicative of the existence of the blocker. The receiver system further includes a configurable receiver circuit configured to receive the RF input signal and the blocker detection signal, and selectively configure the configurable receiver circuit between a first mode wherein the configurable receiver circuit exhibits first linearity characteristics, and a second mode wherein the configurable receiver circuit exhibits second, different linearity characteristics based on the blocker detection signal.
-
公开(公告)号：US10361739B2
公开(公告)日：2019-07-23
申请号：US15836410
申请日：2017-12-08
Applicant: Intel Corporation
Inventor： Hossein Alavi , Farhana Sheikh , Markus Dominik Mueck , Vladimir Ivanov
Abstract: The disclosure generally relates to a method, apparatus and system for identifying non-compliant radio emissions and for enforcing compliance. In one embodiment, the disclosure relates to a dynamic radiation control of a radio by measuring a signal attribute for an outbound signal having a protocol; comparing the signal attribute with a predefined mask, the predefined mask governed by at least one of a radio location or a signal protocol; and determining whether to transmit the outbound signal.
-
公开(公告)号：US20210075456A1
公开(公告)日：2021-03-11
申请号：US16958813
申请日：2018-01-02
Applicant: INTEL CORPORATION
Inventor： Oner Orhan , Hosein Nikopour , Peter Sagazio , Farhana Sheikh , Junyoung Nam , Shilpa Talwar
IPC: H04B1/16
Abstract: A receiver circuit associated with a communication device is disclosed. The receiver circuit comprises a digital data compression circuit configured to receive a plurality of digital receive signals derived from a plurality of analog receive signals respectively associated with the receiver circuit. The digital data compression circuit is further configured to compress the plurality of digital receive signals to form one or more compressed digital data signals based thereon, to be provided to an input output (I/O) interface associated therewith. In some embodiments, a compressed digital signal dimension associated with the one or more compressed digital data signals is less than a digital signal dimension associated with the plurality of digital receive signals.
-
公开(公告)号：US10713333B2
公开(公告)日：2020-07-14
申请号：US15777249
申请日：2015-12-21
Applicant: Intel Corporation
Inventor： Farhana Sheikh , Ankit Sharma , Jaydeep Kulkarni
Abstract: A calculation circuit for calculating a transform of an input sequence may include a plurality of butterfly computation circuits configured to perform a plurality of butterfly computations and to produce a plurality of outputs during each of a plurality of computation stages, a wired routing network configured to route a first plurality of outputs of the plurality of butterfly computation circuits from a first computation stage of the plurality of computation stages as input to the plurality of butterfly computation circuits during a second computation stage of the plurality of computation stages according to a reconfigurable routing configuration, and routing control circuitry configured to modify the reconfigurable routing configuration for a third computation stage of the plurality of computation stages.
-
-
-
-
-
-
-
-
-
Search Results
20
records
(took 0.02 seconds)
