公开(公告)号：US20190034339A1

公开(公告)日：2019-01-31

申请号：US15851567

申请日：2017-12-21

Applicant: Intel Corporation

Inventor： Michael MESNIER ,  Arun RAGHUNATH ,  Mariusz BARCZAK ,  John KEYS

IPC: G06F12/0815 ,  G06F13/16

CPC classification number: G06F12/0815 ,  G06F12/0802 ,  G06F12/0893 ,  G06F13/16 ,  G06F2212/2515 ,  G06F2212/601 ,  G06F2212/604 ,  G06F2212/608

Abstract: Examples may include techniques to monitor processing of I/O requests of an application being executed by a computing platform by collecting a trace of the I/O requests, the trace including an I/O class of each I/O request; replay the trace and automatically analyze possible cache configuration policies for using a cache during execution of the application by the computing platform; and determine an optimal cache configuration policy for the cache from the possible cache configuration policies. The optimal cache configuration policy may then be applied to use of the cache during subsequent execution of the application by the computing platform, thereby improving performance.

公开(公告)号：US20220229722A1

公开(公告)日：2022-07-21

申请号：US17716769

申请日：2022-04-08

Applicant: Intel Corporation

Inventor： Kapil KARKRA ,  Slawomir PTAK ,  Mariusz BARCZAK

IPC: G06F11/10 ,  G06F3/06

Abstract: High performance parity-based Redundant Array of Independent Disks (RAID) on Zoned Namespaces Solid State Drives (SSD)s with support for high queue depth write Input Output (IO) and Zone Append command is provided in a host system. The host system includes a stripe mapping table to store mappings between parity strips and data strips in stripes on the RAID member SSDs. The host system also includes a Logical to Physical (L2P) table to store data block addresses returned by the Zone Append command.

公开(公告)号：US20190042470A1

公开(公告)日：2019-02-07

申请号：US15910941

申请日：2018-03-02

Applicant: Intel Corporation

Inventor： Mariusz BARCZAK ,  Igor KONOPKO ,  Adam RUTKOWSKI

IPC: G06F12/12 ,  G06F12/0804

Abstract: Examples may include techniques to improve cache performance in a computing system. An eviction service may be used to manage a dirty list and a clean list, set a cache line to hot, set a cache line to clean, set a cache line to dirty, and evict a cache line from the cache. A cache engine may be used to write data into the cache at a cache line, request the eviction service to set the cache line to dirty, and manage a dirty cache lines counter for each chunk of the primary memory. A cleaning thread may be used to determine a dirtiest chunk of a primary memory, get a cache line of the dirtiest chunk, and when the cache line of the dirtiest chunk is dirty, read the cache line to get data from the cache, write the data to primary memory, request the eviction service to set the cache line to clean, and manage the dirty cache lines counters.

公开(公告)号：US20230114771A1

公开(公告)日：2023-04-13

申请号：US18078873

申请日：2022-12-09

Applicant: Intel Corporation

Inventor： Mariusz BARCZAK ,  Jan MUSIAL

IPC: G06F9/455 ,  G06F9/4401

Abstract: Methods and apparatus for target triggered IO classification using a computational storage tunnel. A multi-tier memory and storage scheme employing multiple tiers of memory and storage supporting different Input-Output (IO) classes is implemented in an environment including a compute platform. For an IO storage request originating from an application running on the compute platform, an IO class to be used for the request is determined. The IO storage request is then forwarded to a device implementing a memory or storage tier supporting the IO class or via which a device implementing a memory or storage tier supporting the IO class can be accessed. The storage tiers may include local storage in the platform and/or storage accessed via a fabric or network. The storage tiers may implement different types of memory supporting non-volatile storage, with different performance, capacity, and/or endurance, such as a hot and cold tier.

公开(公告)号：US20230051806A1

公开(公告)日：2023-02-16

申请号：US17979687

申请日：2022-11-02

Applicant: Intel Corporation

Inventor： Kapil KARKRA ,  Wojciech MALIKOWSKI ,  Mariusz BARCZAK ,  Shirish BAHIRAT

IPC: G06F3/06

Abstract: A host Flash Translation Layer (FTL) synchronizes host FTL operations with the drive FTL operations to reduce write amplification and over-provisioning. Embodiments of FTL synchronization map, at the host FTL software (SW) stack level, logical bands in which data is managed, referred to as host bands, to the physical bands on a drive where data is stored. The host FTL tracks validity levels of data managed in host bands to determine validity levels of data stored in corresponding physical bands, and optimizes defragmentation operations (such as garbage collection processes and trim operations) applied by the host FTL SW stack to the physical bands based on the tracked validity levels.

公开(公告)号：US20230139729A1

公开(公告)日：2023-05-04

申请号：US18089717

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Mariusz BARCZAK ,  Wojciech MALIKOWSKI ,  Mateusz KOZLOWSKI ,  Lukasz LASEK ,  Artur PASZKIEWICZ ,  Krzysztof SMOLINSKI

IPC: G06F12/0802

Abstract: To increase the availability of a non-volatile cache for use by workloads, the non-volatile cache is dynamically assigned to workloads. The non-volatile cache assigned to a workload can be reduced or increased on demand. A cache space manager ensures that the physical non-volatile cache is available to be assigned prior to assigning. A workload analyzer recognizes a sequential or random workload and requests to reduce the cache space assigned for the sequential or random workload. The workload analyzer recognizes a locality workload, waits until cache space is available in the non-volatile cache and requests an increase of cache space for the locality workload.

公开(公告)号：US20210279186A1

公开(公告)日：2021-09-09

申请号：US17331101

申请日：2021-05-26

Applicant: Intel Corporation

Inventor： Maksymilian KUNT ,  Piotr WYSOCKI ,  Mariusz BARCZAK

IPC: G06F13/16

Abstract: Dynamically controlled interrupt coalescing is performed by enabling interrupt coalescing when the queue depth of the submission queue is high and disabling interrupt coalescing when the queue depth of the submission queue is low to maintain a required quality of service for a solid state drive. The minimum number of completions in the completion queue to trigger an interrupt is modified based on the queue depth of the submission queue. The minimum number of completions is increased when there is an increase in the queue depth of the submission queue and decreased when there is a decrease in the queue depth of the submission queue.

公开(公告)号：US20180285275A1

公开(公告)日：2018-10-04

申请号：US15476885

申请日：2017-03-31

Applicant: INTEL CORPORATION

Inventor： Mariusz BARCZAK ,  Piotr WYSOCKI

IPC: G06F12/0868 ,  G06F12/0871 ,  G06F12/0891

CPC classification number: G06F12/0868 ,  G06F12/0871 ,  G06F12/0891 ,  G06F2212/222 ,  G06F2212/225

Abstract: Provided are an apparatus, computer program product, and method to perform cache operations in a solid state drive. A cache memory determines whether data for a requested storage address in a primary storage namespace received from a host system is stored at an address in the cache memory namespace to which the requested storage address maps according to a cache mapping scheme. Multiple of the storage addresses in the primary storage map to one address in the cache memory namespace. The cache memory returns to the host system the data at the requested address stored in the cache memory namespace in response to determining that the data for the requested storage address is stored in the cache memory namespace.