公开(公告)号：US10950606B2

公开(公告)日：2021-03-16

申请号：US16318316

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Walid M. Hafez ,  Roman W. Olac-Vaw ,  Chia-Hong Jan

IPC: H01L27/092 ,  H01L21/768 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L23/48 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/417

Abstract: Dual fin endcaps for self-aligned gate edge architectures, and methods of fabricating dual fin endcaps for self-aligned gate edge architectures, are described. In an example, a semiconductor structure includes an I/O device having a first plurality of semiconductor fins disposed above a substrate and protruding through an uppermost surface of a trench isolation layer. A logic device having a second plurality of semiconductor fins is disposed above the substrate and protrudes through the uppermost surface of the trench isolation layer. A gate edge isolation structure is disposed between the I/O device and the logic device. A semiconductor fin of the first plurality of semiconductor fins closest to the gate edge isolation structure is spaced farther from the gate edge isolation structure than a semiconductor fin of the second plurality of semiconductor fins closest to the gate edge isolation structure.

公开(公告)号：US10892261B2

公开(公告)日：2021-01-12

申请号：US16318107

申请日：2016-09-29

Applicant: Intel Corporation

Inventor： Walid M. Hafez ,  Roman W. Olac-Vaw ,  Joodong Park ,  Chen-Guan Lee ,  Chia-Hong Jan

IPC: H01L27/088 ,  H01L27/06 ,  H01L21/8234 ,  H01L49/02 ,  H01L29/66 ,  H01L29/78

Abstract: Metal resistors and self-aligned gate edge (SAGE) architectures having metal resistors are described. In an example, a semiconductor structure includes a plurality of semiconductor fins protruding through a trench isolation region above a substrate. A first gate structure is over a first of the plurality of semiconductor fins. A second gate structure is over a second of the plurality of semiconductor fins. A gate edge isolation structure is laterally between and in contact with the first gate structure and the second gate structure. The gate edge isolation structure is on the trench isolation region and extends above an uppermost surface of the first gate structure and the second gate structure. A metal layer is on the gate edge isolation structure and is electrically isolated from the first gate structure and the second gate structure.

公开(公告)号：US10892192B2

公开(公告)日：2021-01-12

申请号：US15930700

申请日：2020-05-13

Applicant: Intel Corporation

Inventor： Roman W. Olac-Vaw ,  Walid M. Hafez ,  Chia-Hong Jan ,  Pei-Chi Liu

IPC: H01L27/088 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/12 ,  H01L21/84 ,  H01L21/28 ,  H01L23/528 ,  H01L29/49 ,  H01L21/8238 ,  H01L29/66

Abstract: Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.

公开(公告)号：US20190097057A1

公开(公告)日：2019-03-28

申请号：US16203780

申请日：2018-11-29

Applicant: Intel Corporation

Inventor： Neville L. Dias ,  Chia-Hong Jan ,  Walid M. Hafez ,  Roman W. Olac-Vaw ,  Hsu-Yu Chang ,  Ting Chang ,  Rahul Ramaswamy ,  Pei-Chi Liu

IPC: H01L29/78 ,  H01L21/8234 ,  H03D7/16

Abstract: An embodiment includes an apparatus comprising: a non-planar fin having first, second, and third portions each having major and minor axes and each being monolithic with each other; wherein (a) the major axes of the first, second, and third portions are parallel with each other, (b) the major axes of the first and second portions are non-collinear with each other, (c) each of the first, second, and third portions include a node of a transistor selected from the group comprising source, drain, and channel, (e) the first, second, and third portions comprise at least one finFET. Other embodiments are described herein.

公开(公告)号：US10229853B2

公开(公告)日：2019-03-12

申请号：US14914179

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Roman W. Olac-Vaw ,  Walid M. Hafez ,  Chia-Hong Jan ,  Pei-Chi Liu

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/12 ,  H01L21/28 ,  H01L23/528 ,  H01L29/49 ,  H01L21/84 ,  H01L29/66

Abstract: Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.

公开(公告)号：US12191207B2

公开(公告)日：2025-01-07

申请号：US18378983

申请日：2023-10-11

Applicant: Intel Corporation

Inventor： Roman W. Olac-Vaw ,  Walid M. Hafez ,  Chia-Hong Jan ,  Pei-Chi Liu

IPC: H01L27/12 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/528 ,  H01L27/088 ,  H01L29/49 ,  H01L29/78 ,  H01L29/66

Abstract: Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.

公开(公告)号：US11823954B2

公开(公告)日：2023-11-21

申请号：US17720150

申请日：2022-04-13

Applicant: Intel Corporation

Inventor： Roman W. Olac-Vaw ,  Walid M. Hafez ,  Chia-Hong Jan ,  Pei-Chi Liu

IPC: H01L27/12 ,  H01L29/78 ,  H01L27/088 ,  H01L29/49 ,  H01L21/8234 ,  H01L21/84 ,  H01L21/28 ,  H01L21/8238 ,  H01L23/528 ,  H01L29/66

CPC classification number: H01L21/82345 ,  H01L21/28088 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/845 ,  H01L23/5283 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/4966 ,  H01L29/7855 ,  H01L29/66545

Abstract: Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.

公开(公告)号：US10692771B2

公开(公告)日：2020-06-23

申请号：US16253760

申请日：2019-01-22

Applicant: Intel Corporation

Inventor： Roman W. Olac-Vaw ,  Walid M. Hafez ,  Chia-Hong Jan ,  Pei-Chi Liu

IPC: H01L21/8234 ,  H01L27/12 ,  H01L21/84 ,  H01L21/28 ,  H01L23/528 ,  H01L27/088 ,  H01L29/49 ,  H01L21/8238 ,  H01L29/66

Abstract: Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.

公开(公告)号：US10164115B2

公开(公告)日：2018-12-25

申请号：US15127850

申请日：2014-06-27

Applicant: Intel Corporation

Inventor： Neville L. Dias ,  Chia-Hong Jan ,  Walid M. Hafez ,  Roman W. Olac-Vaw ,  Hsu-Yu Chang ,  Ting Chang ,  Rahul Ramaswamy ,  Pei-Chi Liu

IPC: H01L29/78 ,  H03D7/14 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L21/84 ,  H01L27/12 ,  H03D7/16 ,  H01L29/417

Abstract: An embodiment includes an apparatus comprising: a non-planar fin having first, second, and third portions each having major and minor axes and each being monolithic with each other; wherein (a) the major axes of the first, second, and third portions are parallel with each other, (b) the major axes of the first and second portions are non-collinear with each other, (c) each of the first, second, and third portions include a node of a transistor selected from the group comprising source, drain, and channel, (e) the first, second, and third portions comprise at least one finFET. Other embodiments are described herein.

公开(公告)号：US11967615B2

公开(公告)日：2024-04-23

申请号：US15773536

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Hsu-Yu Chang ,  Neville L. Dias ,  Walid M. Hafez ,  Chia-Hong Jan ,  Roman W. Olac-Vaw ,  Chen-Guan Lee

IPC: H01L29/10 ,  H01L21/265 ,  H01L29/66 ,  H01L29/78 ,  H01L29/161 ,  H01L29/165

CPC classification number: H01L29/1054 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/7848 ,  H01L29/161 ,  H01L29/165

Abstract: Embodiments of the present invention are directed to dual threshold voltage (VT) channel devices and their methods of fabrication. In an example, a semiconductor device includes a gate stack disposed on a substrate, the substrate having a first lattice constant. A source region and a drain region are formed on opposite sides of the gate electrode. A channel region is disposed beneath the gate stack and between the source region and the drain region. The source region is disposed in a first recess having a first depth and the drain region disposed in a second recess having a second depth. The first recess is deeper than the second recess. A semiconductor material having a second lattice constant different than the first lattice constant is disposed in the first recess and the second recess.