公开(公告)号：US09728515B2

公开(公告)日：2017-08-08

申请号：US15146423

申请日：2016-05-04

Applicant: Intel Corporation

Inventor： Rubayat Mahmud ,  Saikumar Jayaraman ,  Sriram Muthukumar

IPC: H01L23/00 ,  H01L23/31

CPC classification number: H01L24/05 ,  H01L23/3157 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/02126 ,  H01L2224/0384 ,  H01L2224/03845 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05147 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/1132 ,  H01L2224/1147 ,  H01L2224/11474 ,  H01L2224/1148 ,  H01L2224/11849 ,  H01L2224/13007 ,  H01L2224/13026 ,  H01L2924/00014 ,  H01L2924/351 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: This disclosure relates generally to a wafer having a plurality of semiconductor chips having a major surface, a metal contact positioned on one of the plurality of semiconductor chips and having a side surface and contact surface, the contact surface substantially parallel to the major surface, wherein the contact surface defines a thickness of the metal contact relative to the major surface, an underfill layer abutting the one of the plurality of semiconductor chips and the side surface of the metal contact, the underfill layer having a top surface substantially parallel to the major surface, wherein the top surface of the underfill layer defines a thickness of the underfill layer relative to the major surface, the thickness of the underfill layer being not greater than the thickness of the metal contact, and a solder bump formed in electrical contact with the contact surface of the metal contact.

公开(公告)号：US20160247774A1

公开(公告)日：2016-08-25

申请号：US15146423

申请日：2016-05-04

Applicant: Intel Corporation

Inventor： Rubayat Mahmud ,  Saikumar Jayaraman ,  Sriram Muthukumar

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L23/3157 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/02126 ,  H01L2224/0384 ,  H01L2224/03845 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05147 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/1132 ,  H01L2224/1147 ,  H01L2224/11474 ,  H01L2224/1148 ,  H01L2224/11849 ,  H01L2224/13007 ,  H01L2224/13026 ,  H01L2924/00014 ,  H01L2924/351 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: This disclosure relates generally to a wafer having a plurality of semiconductor chips having a major surface, a metal contact positioned on one of the plurality of semiconductor chips and having a side surface and contact surface, the contact surface substantially parallel to the major surface, wherein the contact surface defines a thickness of the metal contact relative to the major surface, an underfill layer abutting the one of the plurality of semiconductor chips and the side surface of the metal contact, the underfill layer having a top surface substantially parallel to the major surface, wherein the top surface of the underfill layer defines a thickness of the underfill layer relative to the major surface, the thickness of the underfill layer being not greater than the thickness of the metal contact, and a solder bump formed in electrical contact with the contact surface of the metal contact.

Abstract translation: 本公开总体上涉及具有多个具有主表面的半导体芯片的晶片，位于多个半导体芯片之一上的金属触点，并且具有侧表面和接触表面，该接触表面基本上平行于主表面，其中 所述接触表面限定所述金属接触件相对于所述主表面的厚度，底部填充层邻接所述多个半导体芯片中的一个和所述金属接触件的侧表面，所述底部填充层具有基本上平行于所述主表面的顶表面 其中所述底部填充层的顶表面相对于所述主表面限定所述底部填充层的厚度，所述底部填充层的厚度不大于所述金属接触件的厚度，以及形成为与所述触点电接触的焊料凸块 表面的金属接触。

公开(公告)号：US11217516B2

公开(公告)日：2022-01-04

申请号：US16231238

申请日：2018-12-21

Applicant: INTEL CORPORATION

Inventor： Sriram Muthukumar ,  Charles A. Gealer

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18 ,  H01L25/00 ,  H01L25/16

Abstract: A stacked-chip apparatus includes a package substrate and an interposer with a chip stack disposed with a standoff that matches the interposer. A package-on-package stacked-chip apparatus includes a top package disposed on the interposer.