公开(公告)号：US20200343194A1

公开(公告)日：2020-10-29

申请号：US16393304

申请日：2019-04-24

Applicant: Intel Corporation

Inventor： Khang Choong YONG ,  Ying Ern HO ,  Yun Rou LIM ,  Wil Choon SONG ,  Stephen HALL

IPC: H01L23/552 ,  H01L23/66 ,  H01L23/00

Abstract: Embodiments include package substrates and method of forming the package substrates. A package substrate includes a dielectric over a conductive layer, and a conductive line on the dielectric. The package substrate includes a plurality of conductive bumps on a surface of the conductive line, where the conductive bumps are conductively coupled to the conductive line, and a solder resist over the conductive line and the dielectric. The surface of the conductive line may be a bottom surface, where the conductive bumps are below the conductive line and conductively coupled to the bottom surface of the conductive line, and where the conductive bumps may be embedded in the dielectric. The surface of the conductive line may be a top surface, where the conductive bumps are above the conductive line and conductively coupled to the top surface of the conductive line, and wherein the conductive bumps are embedded in the solder resist.

公开(公告)号：US20190311963A1

公开(公告)日：2019-10-10

申请号：US15945641

申请日：2018-04-04

Applicant: Intel Corporation

Inventor： Stephen CHRISTIANSON ,  Stephen HALL ,  Emile DAVIES-VENN ,  Dong-Ho HAN ,  Kemal AYGUN ,  Konika GANGULY ,  Jun LIAO ,  M. Reza ZAMANI ,  Cory MASON ,  Kirankumar KAMISETTY

IPC: H01L23/16 ,  H01L23/66 ,  H01L23/00 ,  H01P3/08 ,  H01P11/00 ,  H01L21/48

Abstract: Techniques for fabricating a package substrate and/or a stiffener for a semiconductor package are described. For one technique, a package substrate comprises: a routing layer comprising a dielectric layer. A stiffener may be above the routing layer and a conductive line may be on the routing layer, the conductive line comprising first and second portions, the first portion having a first width, the second portion having a second width, the conductive line extending from a first region of the routing layer to a second region of the routing layer, the first region being under the stiffener, the second region being outside the stiffener, the first portion being on the first region, and the second portion being on the second region. One or more portions of the conductive line can be perpendicular to an edge of the stiffener. The perpendicular portion(s) may comprise a transition between the first and second widths.

公开(公告)号：US20190158024A1

公开(公告)日：2019-05-23

申请号：US16237093

申请日：2018-12-31

Applicant: Intel Corporation

Inventor： Khang Choong YONG ,  Raymond CHONG ,  Ramaswamy PARTHASARATHY ,  Stephen HALL ,  Chin Lee KUAN

IPC: H03B5/32 ,  H03L7/06

CPC classification number: H03B5/32 ,  H03B2200/0088 ,  H03L7/06

Abstract: An apparatus is provided which comprises: a crystal having an input and an output; a first interconnect line having first and second ends, wherein the first end is coupled to the input; a second interconnect line having first and second ends, wherein the first end is coupled to the output; a first capacitor coupled to the input and ground; and a second capacitor coupled to the second end of the second interconnect line. An apparatus is provided which comprises: a high pass filter; a pair of AC coupling capacitors coupled to the high pass filter; a low pass filter coupled to the pair of AC coupling capacitors; and an analog to digital converter (ADC) coupled to the low pass filter.

公开(公告)号：US20200274491A1

公开(公告)日：2020-08-27

申请号：US16714390

申请日：2019-12-13

Applicant: Intel Corporation

Inventor： Khang Choong YONG ,  Raymond CHONG ,  Ramaswamy PARTHASARATHY ,  Stephen HALL ,  Chin Lee KUAN

IPC: H03B5/32 ,  H03L7/06

Abstract: An apparatus is provided which comprises: a crystal having an input and an output; a first interconnect line having first and second ends, wherein the first end is coupled to the input; a second interconnect line having first and second ends, wherein the first end is coupled to the output; a first capacitor coupled to the input and ground; and a second capacitor coupled to the second end of the second interconnect line. An apparatus is provided which comprises: a high pass filter; a pair of AC coupling capacitors coupled to the high pass filter; a low pass filter coupled to the pair of AC coupling capacitors; and an analog to digital converter (ADC) coupled to the low pass filter.

公开(公告)号：US20180123514A1

公开(公告)日：2018-05-03

申请号：US15469499

申请日：2017-03-25

Applicant: INTEL CORPORATION

Inventor： Khang Choong YONG ,  Raymond CHONG ,  Ramaswamy PARTHASARATHY ,  Stephen HALL ,  Chin Lee KUAN

IPC: H03B5/32 ,  H03L7/099

CPC classification number: H03B5/32 ,  H03B2200/0088 ,  H03L7/06

Abstract: An apparatus is provided which comprises: a crystal having an input and an output; a first interconnect line having first and second ends, wherein the first end is coupled to the input; a second interconnect line having first and second ends, wherein the first end is coupled to the output; a first capacitor coupled to the input and ground; and a second capacitor coupled to the second end of the second interconnect line. An apparatus is provided which comprises: a high pass filter; a pair of AC coupling capacitors coupled to the high pass filter; a low pass filter coupled to the pair of AC coupling capacitors; and an analog to digital converter (ADC) coupled to the low pass filter.