公开(公告)号：US20190181080A1

公开(公告)日：2019-06-13

申请号：US16326688

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Bok Eng CHEAH ,  Jackson Chung Peng KONG ,  Khang Choong YONG ,  Po Yin YAW ,  Kok Hou TEH

IPC: H01L23/498 ,  H01L23/538 ,  H01L23/64 ,  H01L25/065 ,  H01L25/10

Abstract: Semiconductor package assemblies and semiconductor packages incorporating an impedance-boosting channel between a transmitter die and a receiver die are described. In an example, a semiconductor package includes a package substrate incorporating the impedance-boosting channel having a first arc segment connected to the transmitter die and a second arc segment connected to the receiver die. The arc segments extend around respective vertical axes passing through a transmitter die electrical bump and a receiver die electrical bump, respectively. Accordingly, the arc segments introduce an inductive circuitry to increase signal integrity of an electrical signal sent from the transmitter die to the receiver die.

公开(公告)号：US20200343194A1

公开(公告)日：2020-10-29

申请号：US16393304

申请日：2019-04-24

Applicant: Intel Corporation

Inventor： Khang Choong YONG ,  Ying Ern HO ,  Yun Rou LIM ,  Wil Choon SONG ,  Stephen HALL

IPC: H01L23/552 ,  H01L23/66 ,  H01L23/00

Abstract: Embodiments include package substrates and method of forming the package substrates. A package substrate includes a dielectric over a conductive layer, and a conductive line on the dielectric. The package substrate includes a plurality of conductive bumps on a surface of the conductive line, where the conductive bumps are conductively coupled to the conductive line, and a solder resist over the conductive line and the dielectric. The surface of the conductive line may be a bottom surface, where the conductive bumps are below the conductive line and conductively coupled to the bottom surface of the conductive line, and where the conductive bumps may be embedded in the dielectric. The surface of the conductive line may be a top surface, where the conductive bumps are above the conductive line and conductively coupled to the top surface of the conductive line, and wherein the conductive bumps are embedded in the solder resist.

公开(公告)号：US20190013303A1

公开(公告)日：2019-01-10

申请号：US15996302

申请日：2018-06-01

Applicant: Intel Corporation

Inventor： Eng Huat GOH ,  Bok Eng CHEAH ,  Jackson Chung Peng KONG ,  Min Suet LIM ,  Khang Choong YONG ,  Howe Yin LOO

IPC: H01L25/16 ,  H01L23/498 ,  H01L23/00 ,  H01L21/50 ,  H01L49/02

Abstract: Embodiments of the present disclosure describe integrated circuit (IC) package assemblies having a stiffener that extends beyond a package substrate outer edge, computing devices incorporating the IC package assemblies, methods for formation of the IC package assemblies, and associated configurations. An IC package assembly may include a package substrate having a first side, a second side opposite the first side, and an outer edge extending between the first side and the second side; an IC die coupled with the first side of the package substrate, where the IC die includes a power terminal; a stiffener coupled with the first side of the package substrate, where the stiffener surrounds the IC die and includes a conductive routing region coupled with the IC die power terminal, and a passive electronic device coupled with the conductive routing region. Other embodiments may be described and/or claimed.

公开(公告)号：US20190215953A1

公开(公告)日：2019-07-11

申请号：US16327453

申请日：2016-10-01

Applicant: Intel Corporation

Inventor： Khang Choong YONG ,  Jackson Chung Peng KONG ,  Bok Eng CHEAH ,  Stephen H. HALL

IPC: H05K1/02

CPC classification number: H05K1/0228 ,  H05K1/0225 ,  H05K1/0253 ,  H05K1/0296 ,  H05K2201/093

Abstract: Embodiments are generally directed to a mutual inductance suppressor for crosstalk immunity enhancement. An embodiment of a printed circuit board includes a first signal trace and a second signal trace on a first layer, wherein the first signal trace and second signal trace are non-intersecting; a second layer below the first layer, the second layer including a voltage reference plane; and a mutual inductance suppressor in the voltage reference plane, the mutual inductance suppressor including a serpentine portion of the voltage reference plane between the first signal trace and the second signal trace.

公开(公告)号：US20190158024A1

公开(公告)日：2019-05-23

申请号：US16237093

申请日：2018-12-31

Applicant: Intel Corporation

Inventor： Khang Choong YONG ,  Raymond CHONG ,  Ramaswamy PARTHASARATHY ,  Stephen HALL ,  Chin Lee KUAN

IPC: H03B5/32 ,  H03L7/06

CPC classification number: H03B5/32 ,  H03B2200/0088 ,  H03L7/06

Abstract: An apparatus is provided which comprises: a crystal having an input and an output; a first interconnect line having first and second ends, wherein the first end is coupled to the input; a second interconnect line having first and second ends, wherein the first end is coupled to the output; a first capacitor coupled to the input and ground; and a second capacitor coupled to the second end of the second interconnect line. An apparatus is provided which comprises: a high pass filter; a pair of AC coupling capacitors coupled to the high pass filter; a low pass filter coupled to the pair of AC coupling capacitors; and an analog to digital converter (ADC) coupled to the low pass filter.

公开(公告)号：US20200314998A1

公开(公告)日：2020-10-01

申请号：US16369555

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Khang Choong YONG ,  Ying Ern HO ,  Wil Choon SONG ,  Yun Rou LIM ,  Telesphor KAMGAING

IPC: H05K1/02 ,  H05K3/02 ,  H05K3/18 ,  H05K1/09

Abstract: Embodiments herein relate to systems, apparatuses, processes or techniques directed to an impedance cushion coupled with a power plane to provide voltage for a system, where the impedance cushion is dimensioned to suppress resonance of the power plane to mitigate RFI or EMI emanating from the power plane during operation.

公开(公告)号：US20200274491A1

公开(公告)日：2020-08-27

申请号：US16714390

申请日：2019-12-13

Applicant: Intel Corporation

Inventor： Khang Choong YONG ,  Raymond CHONG ,  Ramaswamy PARTHASARATHY ,  Stephen HALL ,  Chin Lee KUAN

IPC: H03B5/32 ,  H03L7/06

Abstract: An apparatus is provided which comprises: a crystal having an input and an output; a first interconnect line having first and second ends, wherein the first end is coupled to the input; a second interconnect line having first and second ends, wherein the first end is coupled to the output; a first capacitor coupled to the input and ground; and a second capacitor coupled to the second end of the second interconnect line. An apparatus is provided which comprises: a high pass filter; a pair of AC coupling capacitors coupled to the high pass filter; a low pass filter coupled to the pair of AC coupling capacitors; and an analog to digital converter (ADC) coupled to the low pass filter.

公开(公告)号：US20190208620A1

公开(公告)日：2019-07-04

申请号：US16328535

申请日：2017-08-29

Applicant: Intel Corporation

Inventor： Jackson Chung Peng KONG ,  Bok Eng CHEAH ,  Khang Choong YONG ,  Ramaswamy PARTHASARATHY

IPC: H05K1/02

CPC classification number: H05K1/0222 ,  H05K1/0219 ,  H05K1/0224 ,  H05K2201/0707 ,  H05K2201/09672

Abstract: Embodiments are generally directed to 3D high-inductive ground plane for crosstalk reduction. An embodiment of a printed circuit board includes a first signal trace and a second signal trace on a first layer, wherein the first signal trace and second signal trace are non-intersecting; a second layer below the first layer; a third layer below the second layer; and a three-dimensional (3D) ground plane, the 3D ground plane including a first plurality of segments on the third layer, a second plurality of segments on the second layer, and a plurality of metal vias to connect the first plurality of segments and the second plurality of segments in the ground plane.

公开(公告)号：US20190131257A1

公开(公告)日：2019-05-02

申请号：US16093828

申请日：2016-06-15

Applicant: Intel Corporation

Inventor： Jackson Chung Peng KONG ,  Bok Eng CHEAH ,  Khang Choong YONG ,  Howard Lincoln HECK

IPC: H01L23/66 ,  H01L21/48 ,  H01L23/498

Abstract: Semiconductor packages including a lateral interconnect having an arc segment to increase self-inductance of a signal line is described. In an example, the lateral interconnect includes a circular segment extending around an interconnect pad. The circular segment may extend around a vertical axis of a vertical interconnect to introduce an inductive circuitry to compensate for an impedance mismatch of the vertical interconnect.

公开(公告)号：US20180123514A1

公开(公告)日：2018-05-03

申请号：US15469499

申请日：2017-03-25

Applicant: INTEL CORPORATION

Inventor： Khang Choong YONG ,  Raymond CHONG ,  Ramaswamy PARTHASARATHY ,  Stephen HALL ,  Chin Lee KUAN

IPC: H03B5/32 ,  H03L7/099

CPC classification number: H03B5/32 ,  H03B2200/0088 ,  H03L7/06

Abstract: An apparatus is provided which comprises: a crystal having an input and an output; a first interconnect line having first and second ends, wherein the first end is coupled to the input; a second interconnect line having first and second ends, wherein the first end is coupled to the output; a first capacitor coupled to the input and ground; and a second capacitor coupled to the second end of the second interconnect line. An apparatus is provided which comprises: a high pass filter; a pair of AC coupling capacitors coupled to the high pass filter; a low pass filter coupled to the pair of AC coupling capacitors; and an analog to digital converter (ADC) coupled to the low pass filter.