公开(公告)号：US20220132654A1

公开(公告)日：2022-04-28

申请号：US17353866

申请日：2021-06-22

Applicant: Intel Corporation

Inventor： Vishram Shriram PANDIT ,  Neel Harkishin BHATIA ,  Rajiv PANIGRAHI ,  Ramaswamy PARTHASARATHY ,  Satish RAMACHANDRA ,  Ajay SHARMA ,  Manish SHARMA ,  Vaibhavdeep SINGH ,  Ravichandra TUNGANI CHIKKABASAVAIAH ,  Jayprakash THAKUR

IPC: H05K1/02 ,  H01P3/10

Abstract: A wave launcher may include a printed circuit board (PCB) that includes a pin that receives a radio frequency (RF) signal. The wave launcher may include a cylinder configured to be electrically coupled to the pin and define an opening. The cylinder may receive the RF signal from the pin, form a transition from coplanar to Goubau line structure with a plate, and generate the surface wave. The wave launcher may include an insulator configured to be physically positioned within the opening and between the cylinder and a power line. The insulator may mechanically isolate the cylinder from the power line and permit the cylinder to launch the surface wave on the power line. The wave launcher may include the plate electrically coupled to a pad and may provide a reference for the pin and the cylinder. The pin and the cylinder may be physically positioned proximate the plate.

公开(公告)号：US20240186206A1

公开(公告)日：2024-06-06

申请号：US18438450

申请日：2024-02-10

Applicant: Intel Corporation

Inventor： Satish PRATHABAN ,  Ramaswamy PARTHASARATHY ,  Biswajit PATRA ,  Tongyan ZHAI ,  Jeff KU ,  Min Suet LIM ,  Yi HUANG ,  Kai XIAO ,  Gene F. YOUNG ,  Weimin SHI

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/427 ,  H01L25/065 ,  H01L25/18 ,  H05K1/02

CPC classification number: H01L23/367 ,  H01L23/427 ,  H01L25/0655 ,  H01L25/18 ,  H05K1/0203 ,  H05K1/0262 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2924/1427 ,  H01L2924/15311

Abstract: Systems, apparatuses and methods may provide for technology that includes a voltage regulator, a board assembly including a die and a circuit board electrically coupled to a first side of the die, and a thermal dissipation assembly thermally and electrically coupled to a second side of the die, wherein the thermal dissipation assembly is further electrically coupled to the voltage regulator. In one example, the thermal dissipation assembly includes a vapor chamber and the technology further includes a plurality of copper plates electrically coupled to the voltage regulator and a package substrate containing the die, wherein the plurality of copper plates are further thermally coupled to the vapor chamber.

公开(公告)号：US20200033401A1

公开(公告)日：2020-01-30

申请号：US16045242

申请日：2018-07-25

Applicant: Intel Corporation

Inventor： Ramaswamy PARTHASARATHY ,  Vikas RAO ,  Praveen PAI

IPC: G01R31/28 ,  G01K11/12 ,  H05K7/20 ,  H05K1/02

Abstract: Embodiments include a method of stress testing an electronics package with components that include a visual indicator. In an embodiment, the method comprises populating a plurality of components on an electronics package. In an embodiment, the plurality of components each comprise a visual indicator that is responsive to heat. In an embodiment, the method further comprises stress testing the electronics package and categorizing the plurality of components based on the visual indicators. In an embodiment, the method may further comprise modifying the plurality of components.

公开(公告)号：US20190158024A1

公开(公告)日：2019-05-23

申请号：US16237093

申请日：2018-12-31

Applicant: Intel Corporation

Inventor： Khang Choong YONG ,  Raymond CHONG ,  Ramaswamy PARTHASARATHY ,  Stephen HALL ,  Chin Lee KUAN

IPC: H03B5/32 ,  H03L7/06

CPC classification number: H03B5/32 ,  H03B2200/0088 ,  H03L7/06

Abstract: An apparatus is provided which comprises: a crystal having an input and an output; a first interconnect line having first and second ends, wherein the first end is coupled to the input; a second interconnect line having first and second ends, wherein the first end is coupled to the output; a first capacitor coupled to the input and ground; and a second capacitor coupled to the second end of the second interconnect line. An apparatus is provided which comprises: a high pass filter; a pair of AC coupling capacitors coupled to the high pass filter; a low pass filter coupled to the pair of AC coupling capacitors; and an analog to digital converter (ADC) coupled to the low pass filter.

公开(公告)号：US20200274491A1

公开(公告)日：2020-08-27

申请号：US16714390

申请日：2019-12-13

Applicant: Intel Corporation

Inventor： Khang Choong YONG ,  Raymond CHONG ,  Ramaswamy PARTHASARATHY ,  Stephen HALL ,  Chin Lee KUAN

IPC: H03B5/32 ,  H03L7/06

Abstract: An apparatus is provided which comprises: a crystal having an input and an output; a first interconnect line having first and second ends, wherein the first end is coupled to the input; a second interconnect line having first and second ends, wherein the first end is coupled to the output; a first capacitor coupled to the input and ground; and a second capacitor coupled to the second end of the second interconnect line. An apparatus is provided which comprises: a high pass filter; a pair of AC coupling capacitors coupled to the high pass filter; a low pass filter coupled to the pair of AC coupling capacitors; and an analog to digital converter (ADC) coupled to the low pass filter.

公开(公告)号：US20190208620A1

公开(公告)日：2019-07-04

申请号：US16328535

申请日：2017-08-29

Applicant: Intel Corporation

Inventor： Jackson Chung Peng KONG ,  Bok Eng CHEAH ,  Khang Choong YONG ,  Ramaswamy PARTHASARATHY

IPC: H05K1/02

CPC classification number: H05K1/0222 ,  H05K1/0219 ,  H05K1/0224 ,  H05K2201/0707 ,  H05K2201/09672

Abstract: Embodiments are generally directed to 3D high-inductive ground plane for crosstalk reduction. An embodiment of a printed circuit board includes a first signal trace and a second signal trace on a first layer, wherein the first signal trace and second signal trace are non-intersecting; a second layer below the first layer; a third layer below the second layer; and a three-dimensional (3D) ground plane, the 3D ground plane including a first plurality of segments on the third layer, a second plurality of segments on the second layer, and a plurality of metal vias to connect the first plurality of segments and the second plurality of segments in the ground plane.

公开(公告)号：US20180123514A1

公开(公告)日：2018-05-03

申请号：US15469499

申请日：2017-03-25

Applicant: INTEL CORPORATION

Inventor： Khang Choong YONG ,  Raymond CHONG ,  Ramaswamy PARTHASARATHY ,  Stephen HALL ,  Chin Lee KUAN

IPC: H03B5/32 ,  H03L7/099

CPC classification number: H03B5/32 ,  H03B2200/0088 ,  H03L7/06

Abstract: An apparatus is provided which comprises: a crystal having an input and an output; a first interconnect line having first and second ends, wherein the first end is coupled to the input; a second interconnect line having first and second ends, wherein the first end is coupled to the output; a first capacitor coupled to the input and ground; and a second capacitor coupled to the second end of the second interconnect line. An apparatus is provided which comprises: a high pass filter; a pair of AC coupling capacitors coupled to the high pass filter; a low pass filter coupled to the pair of AC coupling capacitors; and an analog to digital converter (ADC) coupled to the low pass filter.