公开(公告)号：US20220358072A1

公开(公告)日：2022-11-10

申请号：US17874117

申请日：2022-07-26

Applicant: Intel Corporation

Inventor： George VERGIS ,  Xiang LI ,  Jun LIAO ,  Anthony M. CONSTANTINE ,  Min Suet LIM ,  Tongyan ZHAI ,  Konika GANGULY

IPC: G06F13/40 ,  G06F12/06

Abstract: A memory module adapter card can adapt multiple compression-attached memory modules (CAMMs) to a dual inline memory module (DIMM) connector. Multiplexer circuitry on the adapter card enables multiplexing data amongst the memory modules attached to the adapter card during a same burst access sequence.

公开(公告)号：US20190229473A1

公开(公告)日：2019-07-25

申请号：US16370665

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Jaejin LEE ,  Jun LIAO ,  Xiang LI ,  Christopher E. COX

IPC: H01R13/6595 ,  H01R13/6581 ,  H05K9/00 ,  H01R12/72 ,  H05K1/11

Abstract: A device includes a printed circuit board (PCB) and a shield for the PCB. The shield can reduce high frequency electromagnetic frequency (EMF) noise generated by one or more components of the PCB. The PCB includes pads to interface with a corresponding connector. For example, for a dual inline memory module (DIMM) PCB, the PCB includes pads to insert into a DIMM connector. The shield includes a gap in its perimeter that aligns with clips in the corresponding connector. The gaps will correspond to similar features of the PCB that interface with the corresponding connector to allow the shield to attach to the PCB. The shield includes lock fingers to extend from a connector-facing edge of the shield to interface with the corresponding connector to align the shield with the corresponding connector.

公开(公告)号：US20230007775A1

公开(公告)日：2023-01-05

申请号：US17871542

申请日：2022-07-22

Applicant: Intel Corporation

Inventor： Xiang LI ,  Konika GANGULY ,  Tongyan ZHAI ,  George VERGIS ,  Anthony M. CONSTANTINE ,  Jun LIAO

IPC: H05K1/18 ,  H05K1/11

Abstract: Methods and apparatus for GDDR (Graphics Double Date Rate) memory expander using compression mount technology (CMT) connectors. A CMT connector with a dedicated pinout for GDDR-based memory is provided that enables end users and manufacturers to change the amount of GDDR memory provided with a GPU card, accelerator card, or apparatus having other form factors. Memory could also be replaced in the event of a failure. In addition, embodiments are disclosed that support a split channel concept where there could be multiple devices (e.g., GDDR modules) with dedicated signals routed to each module.

公开(公告)号：US20220360002A1

公开(公告)日：2022-11-10

申请号：US17871611

申请日：2022-07-22

Applicant: Intel Corporation

Inventor： Xiang LI ,  Konika GANGULY ,  Tongyan ZHAI ,  George VERGIS ,  Anthony M. CONSTANTINE ,  Jun LIAO

IPC: H01R12/72 ,  G06F1/18 ,  H01R13/24

Abstract: Methods and apparatus for differential I/O (input/output) cards using compression mount technology (CMT) connectors. Assemblies include a CMT connector having an array of spring-loaded pins or contacts that are configured to contact respective CMT contact pads on a pair of printed circuit board (PCBs), such as an add-in card (AIC) and a motherboard. Stacked assemblies are also disclosed including multiple CMT AIC or PCIe modules communicatively coupled using on module CMT connectors. The connector solutions may be used for AICs without changing the overall PCB form factor outline of existing AICs employing edge connectors. Under a stacked assembly of multiple CMT PCIe modules interconnected by on module CMT connectors, wiring in the PCBs is configured to provide signaling supporting multi-lane PCIe or CXL links for each CMT PCIe module. The CMT connector approach also is scalable and can support more pins/contacts to facilitate additional I/O bandwidth.

公开(公告)号：US20200219825A1

公开(公告)日：2020-07-09

申请号：US16824544

申请日：2020-03-19

Applicant: Intel Corporation

Inventor： Jaejin LEE ,  Christopher E. COX ,  Jun LIAO ,  Xiang LI

IPC: H01L23/552 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00

Abstract: A memory device includes a grounded molding. The memory device includes a substrate having a first surface for a memory die, where the substrate has ground vias through substrate to connect to a ground reference. The substrate has a ball grid array (BGA) on the opposite surface, including perimeter balls to connect to ground connections. The grounded molding includes an electrically conductive epoxy mold to cover the memory die, where the electrical conductivity of the molding, with the molding grounded can provide radio frequency interference (RFI) shielding.

公开(公告)号：US20230006374A1

公开(公告)日：2023-01-05

申请号：US17899379

申请日：2022-08-30

Applicant: Intel Corporation

Inventor： Min Suet LIM ,  Luis Carlos ALVAREZ MATA ,  Ankita TIWARI ,  Xiang LI ,  Jun LIAO

IPC: H01R12/71 ,  H01L23/00 ,  H01L23/32 ,  H01L23/40 ,  H01L25/065 ,  H01R13/24

Abstract: A system connects a board to a substrate through an interposer board having compressible connectors through the interposer board. The connectors through the interposer board are compression-based connector pins that extends above and below the interposer board to make electrical contact between the board and the substrate. The system can include a plate to secure the board to the substrate and compress the compression-based connectors of the interposer board.

公开(公告)号：US20220361328A1

公开(公告)日：2022-11-10

申请号：US17871686

申请日：2022-07-22

Applicant: Intel Corporation

Inventor： Xiang LI ,  Konika GANGULY ,  Tongyan ZHAI ,  George VERGIS ,  Anthony M. CONSTANTINE ,  Jun LIAO

IPC: H05K1/11 ,  H05K1/18 ,  G06F1/18

Abstract: Power conversion modules using compression mount technology (CMT) connectors and associated apparatus and methods. Assemblies include a CMT connector that includes an array of spring-loaded CMT pins or contacts that are configured to contact respective pads on a pair of printed circuit board (PCBs), such as for VR module card or power conversion module and a motherboard. The power conversion modules in combination with the CMT connectors provide several advantages, including, a common VR module/power conversion module/motherboard footprint across OEM platforms and test hardware, just in time VR module attachment for improved inventory management, removable power delivery solution makes the platform more conducive to debug, in field servicing, and platform upgradable for higher power CPU/GPU/XPU.

公开(公告)号：US20190311963A1

公开(公告)日：2019-10-10

申请号：US15945641

申请日：2018-04-04

Applicant: Intel Corporation

Inventor： Stephen CHRISTIANSON ,  Stephen HALL ,  Emile DAVIES-VENN ,  Dong-Ho HAN ,  Kemal AYGUN ,  Konika GANGULY ,  Jun LIAO ,  M. Reza ZAMANI ,  Cory MASON ,  Kirankumar KAMISETTY

IPC: H01L23/16 ,  H01L23/66 ,  H01L23/00 ,  H01P3/08 ,  H01P11/00 ,  H01L21/48

Abstract: Techniques for fabricating a package substrate and/or a stiffener for a semiconductor package are described. For one technique, a package substrate comprises: a routing layer comprising a dielectric layer. A stiffener may be above the routing layer and a conductive line may be on the routing layer, the conductive line comprising first and second portions, the first portion having a first width, the second portion having a second width, the conductive line extending from a first region of the routing layer to a second region of the routing layer, the first region being under the stiffener, the second region being outside the stiffener, the first portion being on the first region, and the second portion being on the second region. One or more portions of the conductive line can be perpendicular to an edge of the stiffener. The perpendicular portion(s) may comprise a transition between the first and second widths.

公开(公告)号：US20190102331A1

公开(公告)日：2019-04-04

申请号：US15719742

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Xiang LI ,  Yunhui CHU ,  Jun LIAO ,  George VERGIS ,  James A. McCALL ,  Charles C. PHARES ,  Konika GANGULY ,  Qin LI

IPC: G06F13/16 ,  G11C5/06 ,  G11C5/04 ,  G06F1/18 ,  H01R12/73

CPC classification number: G06F13/1694 ,  G06F1/185 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C7/10 ,  H01R12/73

Abstract: A method is described. The method includes receiving DDR memory channel signals from a motherboard through a larger DIMM motherboard connector. The method includes routing the signals to one of first and second smaller form factor connectors. The method includes sending the DDR memory channel signals to a DIMM that is connected to the one of the first and second smaller form factor connectors.

公开(公告)号：US20240028531A1

公开(公告)日：2024-01-25

申请号：US18375472

申请日：2023-09-30

Applicant: Intel Corporation

Inventor： John R. DREW ,  James A. McCALL ,  Tongyan ZHAI ,  Jun LIAO ,  Min Suet LIM ,  Shigeki TOMISHIMA

IPC: G06F13/16 ,  G06F13/40

CPC classification number: G06F13/1694 ,  G06F13/1689 ,  G06F13/4022

Abstract: A memory subsystem triggers dynamic switching for memory devices to provide access to active memory devices and prevent access to inactive memory devices. Dynamic switching enables a single bus to switch between multiple memory devices whose capacity otherwise exceeds the capacity of the single bus. A switch can be mounted in a memory module or directly on a motherboard alongside the memory devices. A memory controller can toggle a chip select signal as a single control signal to drive the switch. Each switch includes pairs of field effect transistors (FETs), including any of CMOS, NMOS and PMOS FETs. The switch electrically isolates inactive memory devices to prevent access without the need to electrically short the devices.