公开(公告)号：US20150187436A1

公开(公告)日：2015-07-02

申请号：US14320164

申请日：2014-06-30

Applicant: INTEL CORPORATION

Inventor： Bruce QUERBACH ,  William K. LUI ,  David G. ELLIS ,  David J. ZIMMERMAN ,  Theodore Z. SCHOENBORN ,  Christopher W. HAMPSON ,  Ifar WAN ,  Yulan ZHANG

IPC: G11C29/10 ,  G06F11/27 ,  G06F11/263

CPC classification number: G11C29/38 ,  G06F11/263 ,  G06F11/27 ,  G11C11/406 ,  G11C29/10 ,  G11C29/1201 ,  G11C29/16 ,  G11C29/18 ,  G11C29/20 ,  G11C29/36 ,  G11C29/4401 ,  G11C29/72 ,  G11C29/78 ,  G11C29/783 ,  G11C2029/1202 ,  G11C2029/1204 ,  G11C2029/1206 ,  G11C2029/1208 ,  G11C2029/3602 ,  G11C2029/4402

Abstract: In accordance with the present description, a device includes an internal defect detection and repair circuit which includes a self-test logic circuit built in within the device and a self-repair logic circuit also built in within the device. In one embodiment, the built in self-test logic circuit may be configured to automatically identify defective memory cells in a memory. Upon identifying one or more defective memory cells, the built in self-repair logic circuit may be configured to automatically repair the defective memory cells by replacing defective cells with spare cells within the memory. In one embodiment, data patterns are generated as a function of memory addresses and periodic address offsets. Other aspects are described herein.

Abstract translation: 根据本说明书，装置包括内部缺陷检测和修复电路，其包括内置于装置内的自检逻辑电路和内置在装置内的自修复逻辑电路。 在一个实施例中，内置自检逻辑电路可以被配置为自动识别存储器中的有缺陷的存储器单元。 在识别一个或多个有缺陷的存储器单元时，内置的自修复逻辑电路可以被配置为通过用存储器内的备用单元替换有缺陷的单元来自动修复有缺陷的存储器单元。 在一个实施例中，作为存储器地址和周期性地址偏移的函数产生数据模式。 本文描述了其它方面。

公开(公告)号：US20180174639A1

公开(公告)日：2018-06-21

申请号：US15835050

申请日：2017-12-07

Applicant: Intel Corporation

Inventor： Kuljit S. BAINS ,  John B. HALBERT ,  Christopher P. MOZAK ,  Theodore Z. SCHOENBORN ,  Zvika GREENFIELD

IPC: G11C11/4091 ,  G11C11/406 ,  G06F3/06

CPC classification number: G11C11/4091 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0673 ,  G06F2212/7211 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40618 ,  G11C11/40622

Abstract: A memory controller issues a targeted refresh command. A specific row of a memory device can be the target of repeated accesses. When the row is accessed repeatedly within a time threshold (also referred to as “hammered” or a “row hammer event”), physically adjacent row (a “victim” row) may experience data corruption. The memory controller receives an indication of a row hammer event, identifies the row associated with the row hammer event, and sends one or more commands to the memory device to cause the memory device to perform a targeted refresh that will refresh the victim row.

公开(公告)号：US20170084351A1

公开(公告)日：2017-03-23

申请号：US15368402

申请日：2016-12-02

Applicant: INTEL CORPORATION

Inventor： Bruce QUERBACH ,  William K. LUI ,  David G. ELLIS ,  David J. ZIMMERMAN ,  Theodore Z. SCHOENBORN ,  Christopher W. HAMPSON ,  Ifar WAN ,  Yulan ZHANG

IPC: G11C29/38 ,  G11C29/44 ,  G11C29/36

CPC classification number: G11C29/38 ,  G06F11/263 ,  G06F11/27 ,  G11C11/406 ,  G11C29/10 ,  G11C29/1201 ,  G11C29/16 ,  G11C29/18 ,  G11C29/20 ,  G11C29/36 ,  G11C29/4401 ,  G11C29/72 ,  G11C29/78 ,  G11C29/783 ,  G11C2029/1202 ,  G11C2029/1204 ,  G11C2029/1206 ,  G11C2029/1208 ,  G11C2029/3602 ,  G11C2029/4402

Abstract: In accordance with the present description, a device includes an internal defect detection and repair circuit which includes a self-test logic circuit built in within the device and a self-repair logic circuit also built in within the device. In one embodiment, the built in self-test logic circuit may be configured to automatically identify defective memory cells in a memory. Upon identifying one or more defective memory cells, the built in self-repair logic circuit may be configured to automatically repair the defective memory cells by replacing defective cells with spare cells within the memory. In one embodiment, data patterns are generated as a function of memory addresses and periodic address offsets. Other aspects are described herein.

公开(公告)号：US20170213585A1

公开(公告)日：2017-07-27

申请号：US15372031

申请日：2016-12-07

Applicant: Intel Corporation

Inventor： Theodore Z. SCHOENBORN ,  Christopher P. MOZAK

IPC: G11C11/4093 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4096

CPC classification number: G11C11/4093 ,  G06F13/4072 ,  G06F13/4086 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/06 ,  G11C29/56 ,  G11C2029/0401

Abstract: A memory subsystem empirically tests performance parameters of I/O with a memory device. Based on the empirical testing, the memory subsystem can set the performance parameters specific to the system in which the memory subsystem is included. A test system performs the testing. For each of multiple different settings for multiple different I/O circuit parameters, the test system sets a value for each I/O circuit parameter, generates test traffic to stress test the memory device with the parameter value(s), and measures an operating margin for the I/O performance characteristic. The test system further executes a search function to determine values for each I/O circuit parameter at which the operating margin meets a minimum threshold and performance of at least one of the I/O circuit parameters is increased. The memory subsystem sets runtime values for the I/O circuit parameters based on the search function.

公开(公告)号：US20170076779A1

公开(公告)日：2017-03-16

申请号：US15363399

申请日：2016-11-29

Applicant: Intel Corporation

Inventor： Kuljit S. BAINS ,  John B. HALBERT ,  Christopher P. MOZAK ,  Theodore Z. SCHOENBORN ,  Zvika GREENFIELD

IPC: G11C11/4091 ,  G06F3/06 ,  G11C11/406

CPC classification number: G11C11/4091 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0673 ,  G06F2212/7211 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40618 ,  G11C11/40622

Abstract: A memory controller issues a targeted refresh command. A specific row of a memory device can be the target of repeated accesses. When the row is accessed repeatedly within a time threshold (also referred to as “hammered” or a “row hammer event”), physically adjacent row (a “victim” row) may experience data corruption. The memory controller receives an indication of a row hammer event, identifies the row associated with the row hammer event, and sends one or more commands to the memory device to cause the memory device to perform a targeted refresh that will refresh the victim row.

Abstract translation: 内存控制器发出目标刷新命令。 存储器件的特定行可以是重复访问的目标。 当行在时间阈值（也称为“锤击”或“行锤事件”）中重复访问时，物理上相邻的行（“受害者”行）可能会遭遇数据损坏。 存储器控制器接收行敲击事件的指示，识别与行锤事件相关联的行，并且将一个或多个命令发送到存储器设备，以使存储器设备执行将刷新受害者行的目标刷新。