公开(公告)号：US20220004468A1

公开(公告)日：2022-01-06

申请号：US17479267

申请日：2021-09-20

Applicant: Intel Corporation

Inventor： Thomas Willhalm ,  Francesc Guim Bernat ,  Karthik Kumar ,  Rita Gupta ,  Mark Schmisseur ,  Dimitrios Ziakas

IPC: G06F11/20 ,  G06F11/14 ,  G06F9/50 ,  G06F9/445 ,  G06F12/14

Abstract: An embodiment of an electronic apparatus may comprise one or more substrates, and a controller coupled to the one or more substrates, the controller to allocate a first secure portion of a pooled memory to a first instantiation of an application on a first node, and circuitry coupled to the one or more substrates and the controller, the circuitry to provide a failover interface for a second instantiation of the application on a second node to access the first secure portion of the pooled memory in the event of a failure of the first node. Other embodiments are disclosed and claimed.

公开(公告)号：US11157642B2

公开(公告)日：2021-10-26

申请号：US16143724

申请日：2018-09-27

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Mark Schmisseur ,  Kshitij Doshi ,  Kapil Sood ,  Tarun Viswanathan

IPC: G06F21/62 ,  G06F21/60 ,  H04L9/08 ,  H04L29/08 ,  H04W12/08 ,  H04W12/02 ,  H04L29/06

Abstract: An embodiment of a semiconductor apparatus may include technology to receive data with a unique identifier, and bypass encryption logic of a media controller based on the unique identifier. Other embodiments are disclosed and claimed.

公开(公告)号：US10402124B2

公开(公告)日：2019-09-03

申请号：US15474044

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Mark Schmisseur ,  Karthik Kumar ,  Thomas Willhalm ,  Lidia Warnes

IPC: G06F3/06 ,  G06F9/50

Abstract: The present disclosure relates to a dynamically composable computing system. The dynamically composable computing system comprises at least one compute sled including a set of respective local computing hardware resources; a plurality of disaggregated memory modules; at least one disaggregated memory acceleration logic configured to perform one or more predefined computations on data stored in one or more of the plurality of disaggregated memory modules; and a resource manager module configured to assemble a composite computing node by associating, in accordance with requirements of a user, at least one of the plurality of disaggregated memory modules with the disaggregated memory acceleration logic to provide at least one accelerated disaggregated memory module and connecting the least one accelerated disaggregated memory module to the compute sled.

公开(公告)号：US10235526B2

公开(公告)日：2019-03-19

申请号：US14975569

申请日：2015-12-18

Applicant: INTEL CORPORATION

Inventor： Asher Altman ,  Mark Schmisseur

IPC: G06F21/57 ,  G06F9/4401 ,  G06F21/60 ,  G06F21/62 ,  H04L29/06 ,  G06F21/44 ,  G06F21/78 ,  G06F21/81

Abstract: Various embodiments are directed to a system for accessing a self-encrypting drive (SED) upon resuming from a sleep power mode (SPM) state. An SED may be authenticated within a system, for example, upon resuming from a sleep state, based on unwrapping the SED passphrase with a SPM resume passphrase stored in a standby power register to receive power during the SPM state.

公开(公告)号：US20190034383A1

公开(公告)日：2019-01-31

申请号：US15859369

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Mark Schmisseur ,  Dimitrios Ziakas ,  Murugasamy K. Nachimuthu

IPC: G06F15/173 ,  G06F13/16 ,  G06F12/02 ,  G06F12/14

Abstract: Technologies for providing remote access to a shared memory pool include a memory sled. The memory sled includes a memory pool having one or more byte-addressable memory devices and a memory pool controller coupled to the memory pool. The memory pool controller is to produce, for each of a plurality of compute sleds, address space data indicative of addresses of byte-addressable memory in the memory pool accessible to the compute sled, and corresponding permissions associated with the addresses. The memory pool controller is also to provide the address space data to each corresponding compute sled and receive, from a requesting compute sled of the plurality of compute sleds, a memory access request. The memory access request includes an address from the address space data to be accessed. The memory pool controller is also to perform, in response to receiving the memory access request, a memory access operation on the memory pool. Other embodiments are also described and claimed.

公开(公告)号：US20180284996A1

公开(公告)日：2018-10-04

申请号：US15474044

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Mark Schmisseur ,  Karthik Kumar ,  Thomas Willhalm ,  Lidia Warnes

IPC: G06F3/06

CPC classification number: G06F3/067 ,  G06F3/0605 ,  G06F3/0631 ,  G06F9/50

Abstract: The present disclosure relates to a dynamically composable computing system. The dynamically composable computing system comprises at least one compute sled including a set of respective local computing hardware resources; a plurality of disaggregated memory modules; at least one disaggregated memory acceleration logic configured to perform one or more predefined computations on data stored in one or more of the plurality of disaggregated memory modules; and a resource manager module configured to assemble a composite computing node by associating, in accordance with requirements of a user, at least one of the plurality of disaggregated memory modules with the disaggregated memory acceleration logic to provide at least one accelerated disaggregated memory module and connecting the least one accelerated disaggregated memory module to the compute sled.

公开(公告)号：US12019768B2

公开(公告)日：2024-06-25

申请号：US16830703

申请日：2020-03-26

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Mark Schmisseur ,  Thomas Willhalm

IPC: G06F21/60 ,  G06F3/06 ,  H04W12/50

CPC classification number: G06F21/606 ,  G06F3/0604 ,  G06F3/0622 ,  G06F3/0644 ,  G06F3/0659 ,  G06F3/0673 ,  H04W12/50

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to process memory operation requests from a memory controller, and provide a front end interface to remote pooled memory hosted at a near edge device. An embodiment of another electronic apparatus may include local memory and logic communicatively coupled the local memory, the logic to allocate a range of the local memory as remote pooled memory, and provide a back end interface to the remote pooled memory for memory requests from a far edge device. Other embodiments are disclosed and claimed.

公开(公告)号：US11449446B2

公开(公告)日：2022-09-20

申请号：US16936078

申请日：2020-07-22

Applicant: Intel Corporation

Inventor： Thomas M. Slaight ,  Sivakumar Radhakrishnan ,  Mark Schmisseur ,  Pankaj Kumar ,  Saptarshi Mondal ,  Sin S. Tan ,  David C. Lee ,  Marc T. Jones ,  Geetani R. Edirisooriya ,  Bradley A. Burres ,  Brian M. Leitner ,  Kenneth C. Haren ,  Michael T. Klinglesmith ,  Matthew R. Wilcox ,  Eric J. Dahlen

IPC: G06F13/40 ,  G06F13/28 ,  G06F12/0866 ,  G06F3/06 ,  G06F11/10 ,  G06F13/16 ,  G06F13/42 ,  G06F13/10

Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for presentation of direct accessed storage under a logical drive model; for implementing a distributed architecture for cooperative NVM Data protection; data mirroring for consistent SSD latency; for boosting a controller's performance and RAS with DIF support via concurrent RAID processing; for implementing arbitration and resource schemes of a doorbell mechanism, including doorbell arbitration for fairness and prevention of attack congestion; and for implementing multiple interrupt generation using a messaging unit and NTB in a controller through use of an interrupt coalescing scheme.

公开(公告)号：US10990534B2

公开(公告)日：2021-04-27

申请号：US16264447

申请日：2019-01-31

Applicant: Intel Corporation

Inventor： Wei Chen ,  Eswaramoorthi Nallusamy ,  Larisa Novakovsky ,  Mark Schmisseur ,  Eric Rasmussen ,  Stephen Van Doren ,  Yen-Cheng Liu

IPC: G06F12/08 ,  G06F12/0891 ,  G06F12/0802 ,  G06F12/02

Abstract: Techniques and mechanisms for capturing an image of processor state at one node of multiple nodes of a multi-processor platform, where the processor state includes some version of data which the node retrieved from another node of the platform. In an embodiment, a disruption of power is detected when a processor of a first node has a cached version of data which was retrieved from a second node. In response to detection of the disruption, the data is saved to a system memory of the first node as part of an image of the processor's state. The image further comprises address information, corresponding to the data, which indicates a memory location at the second node. In another embodiment, processor state is restored during a boot-up of the node, wherein the state includes the captured version of data which was previously retrieved from the second node.

公开(公告)号：US10581596B2

公开(公告)日：2020-03-03

申请号：US15859367

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Mark Schmisseur ,  Dimitrios Ziakas ,  Murugasamy K. Nachimuthu

IPC: G06F11/00 ,  H04L9/08 ,  G06F3/06 ,  G06F9/50 ,  H04L29/06 ,  H04L29/08 ,  G06F16/25 ,  G06F16/2453 ,  H04L12/861 ,  G11C8/12 ,  G11C29/02 ,  H04L12/24 ,  G11C29/36 ,  G11C29/38 ,  G11C29/44 ,  G06F16/22 ,  G06F16/2455 ,  G06F12/02 ,  G06F12/14 ,  G06F13/16 ,  G06F15/173 ,  G06F13/40 ,  G06F13/42 ,  G06F9/448 ,  G06F9/28 ,  G06F15/16 ,  H04L12/703 ,  H04L12/743 ,  H04L12/801 ,  H04L12/803 ,  H04L12/935 ,  H04L12/931 ,  G06F9/4401 ,  G06F9/445 ,  G06F12/06 ,  G06F16/23 ,  G06F16/248 ,  G06F16/901 ,  G06F16/11 ,  G06F12/0802 ,  G06F12/1045

Abstract: Technologies for managing errors in a remotely accessible memory pool include a memory sled. The memory sled includes a memory pool having one or more byte-addressable memory devices and a memory pool controller coupled to the memory pool. The memory sled is to write test data to a byte-addressable memory region in the memory pool. The memory region is to be accessed by a remote compute sled. The memory sled is also to read data from the memory region to which the test data was written, compare the read data to the test data to determine whether a threshold number of errors are present in the read data, and send, in response to a determination that the threshold number of errors are present in the read data, a notification to the remote compute sled that the memory region is faulty.