公开(公告)号：US12051698B2

公开(公告)日：2024-07-30

申请号：US17030350

申请日：2020-09-23

Applicant: Intel Corporation

Inventor： Daniel G. Ouellette ,  Daniel B. O'Brien ,  Jeffrey S. Leib ,  Orb Acton ,  Lukas Baumgartel ,  Dan S. Lavric ,  Dax M. Crum ,  Oleg Golonzka ,  Tahir Ghani

IPC: H01L27/00 ,  H01L27/092 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/775

CPC classification number: H01L27/0924 ,  H01L29/0673 ,  H01L29/408 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/775

Abstract: Gate-all-around integrated circuit structures having molybdenum nitride metal gates and gate dielectrics with a dipole layer are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, the first gate stack having a P-type conductive layer on a first gate dielectric. The P-type conductive layer includes molybdenum and nitrogen. A second gate stack is over the second vertical arrangement of horizontal nanowires, the second gate stack having an N-type conductive layer on a second gate dielectric.

公开(公告)号：US11018222B1

公开(公告)日：2021-05-25

申请号：US16728088

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： Daniel B. O'Brien ,  Christopher J. Wiegand ,  Lukas M. Baumgartel ,  Oleg Golonzka ,  Dan S. Lavric ,  Daniel B. Bergstrom ,  Jeffrey S. Leib ,  Timothy Michael Duffy ,  Dax M. Crum

IPC: H01L29/06 ,  H01L23/00 ,  B82B1/00

Abstract: Disclosed herein are structures, methods, and assemblies related to metallization in integrated circuit (IC) structures. For example, in some embodiments, an IC structure may include a first nanowire in a metal region and a second nanowire in the metal region. A distance between the first nanowire and the second nanowire may be less than 5 nanometers, and the metal region may include tungsten between the first nanowire and the second nanowire.

公开(公告)号：US12089411B2

公开(公告)日：2024-09-10

申请号：US16910020

申请日：2020-06-23

Applicant: Intel Corporation

Inventor： Tanuj Trivedi ,  Walid M. Hafez ,  Rohan Bambery ,  Daniel B. O'Brien ,  Christopher Alan Nolph ,  Rahul Ramaswamy ,  Ting Chang

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/66 ,  H01L29/792 ,  H01L49/02 ,  H10B43/30

CPC classification number: H10B43/30 ,  H01L28/60 ,  H01L29/40117 ,  H01L29/66795 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/792

Abstract: Embodiments disclosed herein include a semiconductor device and methods of forming such a device. In an embodiment, the semiconductor device comprises a substrate and a transistor on the substrate. In an embodiment, the transistor comprises a first gate electrode, where the first gate electrode is part of a first array of gate electrodes with a first pitch. In an embodiment, the first gate electrode has a first average grain size. In an embodiment, the semiconductor device further comprises a component cell on the substrate. In an embodiment, the component cell comprises a second gate electrode, where the second gate electrode is part of a second array of gate electrodes with a second pitch that is larger than the first pitch. In an embodiment, the second gate electrode has a second average grain size that is larger than the first average grain size.

公开(公告)号：US20210399002A1

公开(公告)日：2021-12-23

申请号：US16910020

申请日：2020-06-23

Applicant: Intel Corporation

Inventor： Tanuj TRIVEDI ,  Walid M. HAFEZ ,  Rohan BAMBERY ,  Daniel B. O'Brien ,  Christopher Alan NOLPH ,  Rahul RAMASWAMY ,  Ting CHANG

IPC: H01L27/11568 ,  H01L49/02 ,  H01L29/78 ,  H01L29/792 ,  H01L21/28 ,  H01L29/66

Abstract: Embodiments disclosed herein include a semiconductor device and methods of forming such a device. In an embodiment, the semiconductor device comprises a substrate and a transistor on the substrate. In an embodiment, the transistor comprises a first gate electrode, where the first gate electrode is part of a first array of gate electrodes with a first pitch. In an embodiment, the first gate electrode has a first average grain size. In an embodiment, the semiconductor device further comprises a component cell on the substrate. In an embodiment, the component cell comprises a second gate electrode, where the second gate electrode is part of a second array of gate electrodes with a second pitch that is larger than the first pitch. In an embodiment, the second gate electrode has a second average grain size that is larger than the first average grain size.