公开(公告)号：US20170237659A1

公开(公告)日：2017-08-17

申请号：US15396497

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： Mark S Birrittella ,  Thomas D. Lovett ,  Todd M. Rimmer

IPC: H04L12/741 ,  H04L5/00 ,  H04L12/801

CPC classification number: H04L45/745 ,  H04L5/0055 ,  H04L45/66 ,  H04L45/74 ,  H04L47/17 ,  H04L47/39 ,  H04L49/25 ,  H04L61/3075 ,  H04Q2213/13215

Abstract: Method, apparatus, and systems for reliably transferring Ethernet packet data over a link layer and facilitating fabric-to-Ethernet and Ethernet-to-fabric gateway operations at matching wire speed and packet data rate. Ethernet header and payload data is extracted from Ethernet frames received at the gateway and encapsulated in fabric packets to be forwarded to a fabric endpoint hosting an entity to which the Ethernet packet is addressed. The fabric packets are divided into flits, which are bundled in groups to form link packets that are transferred over the fabric at the Link layer using a reliable transmission scheme employing implicit ACKnowledgements. At the endpoint, the fabric packet is regenerated, and the Ethernet packet data is de-encapsulated. The Ethernet frames received from and transmitted to an Ethernet network are encoded using 64b/66b encoding, having an overhead-to-data bit ratio of 1:32. Meanwhile, the link packets have the same ratio, including one overhead bit per flit and a 14-bit CRC plus a 2-bit credit return field or sideband used for credit-based flow control.

公开(公告)号：US20220210639A1

公开(公告)日：2022-06-30

申请号：US17548237

申请日：2021-12-10

Applicant: Intel Corporation

Inventor： William R. Magro ,  Todd M. Rimmer ,  Robert J. Woodruff ,  Mark S. Hefty ,  Sayantan Sur

IPC: H04W12/06 ,  G06F9/448 ,  H04L9/40 ,  G06F9/50 ,  H04L49/10 ,  H04L49/20

Abstract: In an embodiment, at least one interface mechanism may be provided. The mechanism may permit, at least in part, at least one process allocate, at least in part, and/or configure, at least in part, at least one network-associated object. Such allocation and/or configuration, at least in part, may be in accordance with at least one parameter set that may correspond, at least in part, to at least one query issued by the at least one process via the mechanism. Many modifications are possible without departing from this embodiment.

公开(公告)号：US20180091332A1

公开(公告)日：2018-03-29

申请号：US15277577

申请日：2016-09-27

Applicant: Intel Corporation

Inventor： Brent R. Rothermel ,  Todd M. Rimmer

IPC: H04L25/03 ,  H04L27/20

CPC classification number: H04L25/03006 ,  G06F11/08 ,  G06F11/14 ,  H04L1/004 ,  H04L1/0047 ,  H04L1/1829

Abstract: Disclosed herein are high performance systems with low latency error correction as well as related devices and methods. In some embodiments, high performance systems may include: central processing units, adapter chips, and switch chips connected via channels, each chip including link level forward error correction and link level replay, where errors at or below a threshold level are corrected by forward error correction and remaining errors are corrected using replay. In some embodiments, high performance systems may include: central processing units, adapter chips, and switch chips connected via channels, each chip including link level forward error correction, link level replay, and a multiplexer for determining which error correction technique to use based on the number of errors and an error threshold level.

公开(公告)号：US11246027B2

公开(公告)日：2022-02-08

申请号：US15280439

申请日：2016-09-29

Applicant: Intel Corporation

Inventor： William R. Magro ,  Todd M. Rimmer ,  Robert J. Woodruff ,  Mark S. Hefty ,  Sayantan Sur

IPC: H04L12/931 ,  H04W12/06 ,  G06F9/448 ,  H04L29/06 ,  G06F9/50 ,  H04L12/933 ,  H04L29/12

Abstract: In an embodiment, at least one interface mechanism may be provided. The mechanism may permit, at least in part, at least one process allocate, at least in part, and/or configure, at least in part, at least one network-associated object. Such allocation and/or configuration, at least in part, may be in accordance with at least one parameter set that may correspond, at least in part, to at least one query issued by the at least one process via the mechanism. Many modifications are possible without departing from this embodiment.

公开(公告)号：US10432586B2

公开(公告)日：2019-10-01

申请号：US15531168

申请日：2014-12-27

Applicant: INTEL CORPORATION

Inventor： Todd M. Rimmer ,  Thomas D. Lovett ,  Alberto J. Munoz

IPC: H04L29/06 ,  H04L12/64 ,  H04L12/823 ,  H04L12/947 ,  H04L29/08

Abstract: Technologies for fabric security include one or more managed network devices coupled to one or more computing nodes via high-speed fabric links. A managed network device enables a port and, while enabling the port, securely determines the node type of the link partner coupled to the port. If the link partner is a computing node, management access is not allowed at the port. The managed network device may allow management access at certain predefined ports, which may be connected to one of more management nodes. Management access may be allowed for additional ports in response to management messages received from the management nodes. The managed network device may check and verify data packet headers received from a compute node at each port. The managed network device may rate-limit management messages received from a compute node at each port. Other embodiments are described and claimed.

公开(公告)号：US10305802B2

公开(公告)日：2019-05-28

申请号：US15396497

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： Mark S. Birrittella ,  Thomas D. Lovett ,  Todd M. Rimmer

IPC: H04L12/741 ,  H04L12/721 ,  H04L12/947 ,  H04L5/00 ,  H04L12/801 ,  H04L29/12

Abstract: Method, apparatus, and systems for reliably transferring Ethernet packet data over a link layer and facilitating fabric-to-Ethernet and Ethernet-to-fabric gateway operations at matching wire speed and packet data rate. Ethernet header and payload data is extracted from Ethernet frames received at the gateway and encapsulated in fabric packets to be forwarded to a fabric endpoint hosting an entity to which the Ethernet packet is addressed. The fabric packets are divided into flits, which are bundled in groups to form link packets that are transferred over the fabric at the Link layer using a reliable transmission scheme employing implicit ACKnowledgements. At the endpoint, the fabric packet is regenerated, and the Ethernet packet data is de-encapsulated. The Ethernet frames received from and transmitted to an Ethernet network are encoded using 64b/66b encoding, having an overhead-to-data bit ratio of 1:32. Meanwhile, the link packets have the same ratio, including one overhead bit per flit and a 14-bit CRC plus a 2-bit credit return field or sideband used for credit-based flow control.

公开(公告)号：US10432582B2

公开(公告)日：2019-10-01

申请号：US15531153

申请日：2014-12-27

Applicant: INTEL CORPORATION

Inventor： Todd M. Rimmer ,  Albert S. Cheng

IPC: H04L29/12 ,  H04L12/64 ,  H04L12/761 ,  H04L12/931 ,  H04L29/06

Abstract: Technologies for scalable local addressing include one or more managed network devices coupled to one or more computing nodes via high-speed fabric links. A computing node may transmit a data packet including a destination local identifier (DLID) that identifies the destination computing node. The DLID may be 32, 24, 20, or 16 bits wide. The managed network device may determine whether the DLID is within a configurable multicast address space and, if so, forward the data packet to a multicast group. The managed network device may also determine whether the DLID is within a configurable collective address space and, if so, perform a collective acceleration operation. The number of top-most bits set in a multicast mask and the number of additional top-most bits set in a collective mask may be configured. Multicast LIDs may be converted between different bit lengths. Other embodiments are described and claimed.

公开(公告)号：US09979566B2

公开(公告)日：2018-05-22

申请号：US15277577

申请日：2016-09-27

Applicant: Intel Corporation

Inventor： Brent R. Rothermel ,  Todd M. Rimmer

IPC: G06F11/08 ,  G06F11/14 ,  H04L25/03 ,  H04L27/20

CPC classification number: H04L25/03006 ,  G06F11/08 ,  G06F11/14 ,  H04L1/004 ,  H04L1/0047 ,  H04L1/1829

Abstract: Disclosed herein are high performance systems with low latency error correction as well as related devices and methods. In some embodiments, high performance systems may include: central processing units, adapter chips, and switch chips connected via channels, each chip including link level forward error correction and link level replay, where errors at or below a threshold level are corrected by forward error correction and remaining errors are corrected using replay. In some embodiments, high performance systems may include: central processing units, adapter chips, and switch chips connected via channels, each chip including link level forward error correction, link level replay, and a multiplexer for determining which error correction technique to use based on the number of errors and an error threshold level.

公开(公告)号：US09479506B2

公开(公告)日：2016-10-25

申请号：US14254609

申请日：2014-04-16

Applicant: Intel Corporation

Inventor： William R. Magro ,  Todd M. Rimmer ,  Robert J. Woodruff ,  Mark S. Hefty ,  Sayantan Sur

IPC: H04W72/04 ,  H04L29/06 ,  G06F9/50 ,  H04W12/06 ,  H04L29/12 ,  G06F9/44

CPC classification number: H04L49/20 ,  G06F9/4488 ,  G06F9/50 ,  H04L49/10 ,  H04L61/103 ,  H04L63/10 ,  H04W12/06

Abstract: In an embodiment, at least one interface mechanism may be provided. The mechanism may permit, at least in part, at least one process allocate, at least in part, and/or configure, at least in part, at least one network-associated object. Such allocation and/or configuration, at least in part, may be in accordance with at least one parameter set that may correspond, at least in part, to at least one query issued by the at least one process via the mechanism. Many modifications are possible without departing from this embodiment.

Abstract translation: 在一个实施例中，可以提供至少一个接口机构。 该机制可以至少部分地允许至少一个过程至少部分地分配和/或配置至少一个网络相关对象。 至少部分地，这样的分配和/​​或配置可以与至少一个可以至少部分地对应于由至少一个进程通过机制发出的至少一个查询的至少一个参数集合进行。 在不脱离本实施例的情况下，可以进行许多修改。