公开(公告)号：US10326711B2

公开(公告)日：2019-06-18

申请号：US15531643

申请日：2014-12-24

Applicant: Intel Corporation

Inventor： Albert S. Cheng ,  Thomas D. Lovett ,  Michael A. Parker ,  Steven F. Hoover ,  Gregory J. Hubbard

IPC: H04L12/933 ,  H04L12/937

Abstract: Apparatuses, methods and storage media associated with multiple multi-drop buses in a switch are provided herein. In some embodiments, the switch may include a multi-drop row bus to transmit a plurality of frames in a row dimension of the matrix switch and a multi-drop column bus to transmit the plurality of frames in a column dimension of the matrix switch. The switch may further include an input port to receive the plurality of frames and an output port to output the plurality of frames from the matrix switch. Other embodiments may be described and/or claimed.

公开(公告)号：US10951526B2

公开(公告)日：2021-03-16

申请号：US15639864

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Albert S. Cheng ,  Michael A. Parker

IPC: H04L12/801 ,  H04L12/835 ,  H04L12/26

Abstract: Technologies for determining a root of congestion include a network switch. The network switch is to operate arbiter units in at least one upstream stage at a packet transfer rate that is greater than a packet transfer rate of an arbiter unit in an output stage, determine whether an input buffer of a remote network switch in communication with the output stage has sustained congestion over a first predefined time period, determine whether an output buffer of the arbiter unit in the output stage has sustained congestion over a second predefined time period, and determine, as a function of whether the input buffer of the remote network switch has sustained congestion and whether the output buffer of the arbiter unit in the output stage has sustained congestion, whether the network switch is a root of congestion.

公开(公告)号：US10757039B2

公开(公告)日：2020-08-25

申请号：US15531688

申请日：2014-12-24

Applicant: Intel Corporation

Inventor： Albert S. Cheng ,  Thomas D. Lovett ,  Michael A. Parker

IPC: H04L12/947 ,  H04L12/835 ,  H04L12/741 ,  H04L12/801 ,  H04L12/935 ,  H04L12/933 ,  H04L12/803

Abstract: Apparatuses, methods and storage medium associated with routing data in a switch are provided. In embodiments, the switch may include route lookup circuitry determine a first set of output ports that are available to send a data packet to a destination node. The lookup circuitry may further select, based on respective congestion levels associated with the first set of output ports, a plurality of output ports for a second set of output ports from the first set of output ports. An input queue of the switch may buffer the data packet and route information associated with the second set of output ports. The switch may further include route selection circuitry to select a destination output port from the second set of output ports, based on updated congestion levels associated with the output ports of the second set of output ports. Other embodiments may be described and/or claimed.

公开(公告)号：US11528229B2

公开(公告)日：2022-12-13

申请号：US16929064

申请日：2020-07-14

Applicant: Intel Corporation

Inventor： Albert S. Cheng ,  Thomas D. Lovett ,  Michael A. Parker

IPC: H04L47/24 ,  H04L47/2425 ,  H04L49/356 ,  H04L47/70 ,  H04L43/0894 ,  H04L45/64 ,  H04L47/283

Abstract: This disclosure describes systems, devices, methods and computer readable media for enhanced network communication for use in higher performance applications including storage, high performance computing (HPC) and Ethernet-based fabric interconnects. In some embodiments, a network controller may include a transmitter circuit configured to transmit packets on a plurality of virtual lanes (VLs), the VLs associated with a defined VL priority and an allocated share of network bandwidth. The network controller may also include a bandwidth monitor module configured to measure bandwidth consumed by the packets and an arbiter module configured to adjust the VL priority based on a comparison of the measured bandwidth to the allocated share of network bandwidth. The transmitter circuit may be further configured to transmit the packets based on the adjusted VL priority.

公开(公告)号：US10432582B2

公开(公告)日：2019-10-01

申请号：US15531153

申请日：2014-12-27

Applicant: INTEL CORPORATION

Inventor： Todd M. Rimmer ,  Albert S. Cheng

IPC: H04L29/12 ,  H04L12/64 ,  H04L12/761 ,  H04L12/931 ,  H04L29/06

Abstract: Technologies for scalable local addressing include one or more managed network devices coupled to one or more computing nodes via high-speed fabric links. A computing node may transmit a data packet including a destination local identifier (DLID) that identifies the destination computing node. The DLID may be 32, 24, 20, or 16 bits wide. The managed network device may determine whether the DLID is within a configurable multicast address space and, if so, forward the data packet to a multicast group. The managed network device may also determine whether the DLID is within a configurable collective address space and, if so, perform a collective acceleration operation. The number of top-most bits set in a multicast mask and the number of additional top-most bits set in a collective mask may be configured. Multicast LIDs may be converted between different bit lengths. Other embodiments are described and claimed.

公开(公告)号：US10715452B2

公开(公告)日：2020-07-14

申请号：US16259228

申请日：2019-01-28

Applicant: Intel Corporation

Inventor： Albert S. Cheng ,  Thomas D. Lovett ,  Michael A. Parker

IPC: H04L12/851 ,  H04L12/931 ,  H04L12/911 ,  H04L12/26 ,  H04L12/715 ,  H04L12/841

Abstract: This disclosure describes systems, devices, methods and computer readable media for enhanced network communication for use in higher performance applications including storage, high performance computing (HPC) and Ethernet-based fabric interconnects. In some embodiments, a network controller may include a transmitter circuit configured to transmit packets on a plurality of virtual lanes (VLs), the VLs associated with a defined VL priority and an allocated share of network bandwidth. The network controller may also include a bandwidth monitor module configured to measure bandwidth consumed by the packets and an arbiter module configured to adjust the VL priority based on a comparison of the measured bandwidth to the allocated share of network bandwidth. The transmitter circuit may be further configured to transmit the packets based on the adjusted VL priority.

公开(公告)号：US10469368B2

公开(公告)日：2019-11-05

申请号：US15554207

申请日：2015-03-28

Applicant: Intel Corporation

Inventor： Albert S. Cheng

IPC: H04L12/721 ,  H04L12/741 ,  H04L12/933 ,  H04L12/707 ,  H04L12/743

Abstract: Generally, this disclosure provides systems, methods and computer readable media for switching systems employing distributed routing tables to provide improved support for multiple network topologies, configurations and routing modes. A routing system of a switch, for routing a packet from an input port of a switch to an output port, may include memory modules to store routing tables configured to store entries, each entry configured to store output port identifiers. The routing system may also include a table address generation module configured to select an entry from the routing tables based in part on a first subset of a Destination Location ID (DLID) associated with the packet. The table address generation module may further be configured to select one or more output ports from the selected entries, the selected output ports based in part on a second subset of the DLID.

公开(公告)号：US10454850B2

公开(公告)日：2019-10-22

申请号：US15531694

申请日：2014-12-24

Applicant: Intel Corporation

Inventor： Albert S. Cheng ,  Thomas D. Lovett ,  Michael S. Parker ,  Steven F. Hoover

IPC: H04L12/933 ,  H04L12/935 ,  H04L12/861 ,  H04L12/64 ,  H04L12/937 ,  H04L12/931

Abstract: Apparatuses, methods and storage medium associated with buffering data in a switch are provided. In embodiments, the switch may include a plurality of queue buffers, a plurality of queues respectively associated with the plurality of queue buffers, a shared buffer, and a queue point controller coupled with the plurality of queue buffers and the shared buffer. In embodiments the queue point controller may be configured to determine an amount of available space in a selected queue buffer of the plurality of queue buffers. The queue point controller may be further configured to allocate at least a portion of the shared buffer to a selected queue that is associated with the selected queue buffer. In embodiments, this allocation may be based on the amount of available space determined in the selected queue buffer. Other embodiments may be described and/or claimed.

公开(公告)号：US20190007317A1

公开(公告)日：2019-01-03

申请号：US15639864

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Albert S. Cheng ,  Michael A. Parker

IPC: H04L12/801 ,  H04L12/835 ,  H04L12/26

Abstract: Technologies for determining a root of congestion include a network switch. The network switch is to operate arbiter units in at least one upstream stage at a packet transfer rate that is greater than a packet transfer rate of an arbiter unit in an output stage, determine whether an input buffer of a remote network switch in communication with the output stage has sustained congestion over a first predefined time period, determine whether an output buffer of the arbiter unit in the output stage has sustained congestion over a second predefined time period, and determine, as a function of whether the input buffer of the remote network switch has sustained congestion and whether the output buffer of the arbiter unit in the output stage has sustained congestion, whether the network switch is a root of congestion.

公开(公告)号：US10911366B2

公开(公告)日：2021-02-02

申请号：US15639816

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Scott S. Diesing ,  Michael A. Parker ,  Albert S. Cheng ,  Nan Ni

IPC: H04L12/54 ,  H04L12/70 ,  H04L12/773 ,  H04L12/803 ,  H04L12/863 ,  H04L12/867 ,  H04L12/869 ,  H04L12/933 ,  H04L12/935

Abstract: Technologies for balancing throughput across input ports include a network switch. The network switch is to generate, for an arbiter unit in a first stage of a hierarchy of stages of arbiter units, turn data indicative of a set of turns in which to transfer packet data from devices connected to input ports of the arbiter unit. The network switch is also to transfer, with the arbiter unit, the packet data from the devices in the set of turns. Additionally, the network switch is to determine weight data indicative of the number of turns represented in the set and provide the weight data from the arbiter unit in the first stage to another arbiter unit in a subsequent stage to cause the arbiter unit in the subsequent stage to allocate a number of turns for the transfer of the packet data from the arbiter unit in the first stage.