公开(公告)号：US20200287006A1

公开(公告)日：2020-09-10

申请号：US16645405

申请日：2017-12-27

Applicant: Intel Corporation

Inventor： Abhishek A. SHARMA ,  Van H. LE ,  Li Huey TAN ,  Tristan TRONIC ,  Benjamin CHU-KUNG

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/786

Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT), which may include a gate electrode above a substrate and a channel layer above the gate electrode. A source electrode may be above the channel layer and adjacent to a source area of the channel layer, and a drain electrode may be above the channel layer and adjacent to a drain area of the channel layer. A passivation layer may be above the channel layer and between the source electrode and the drain electrode, and a top dielectric layer may be above the gate electrode, the channel layer, the source electrode, the drain electrode, and the passivation layer. In addition, an air gap may be above the passivation layer and below the top dielectric layer, and between the source electrode and the drain electrode. Other embodiments may be described and/or claimed.

公开(公告)号：US20200033736A1

公开(公告)日：2020-01-30

申请号：US16045253

申请日：2018-07-25

Applicant: Intel Corporation

Inventor： Robert BRISTOL ,  Guojing ZHANG ,  Tristan TRONIC ,  John MAGANA ,  Chang Ju CHOI ,  Arvind SUNDARAMURTHY ,  Richard SCHENKER

IPC: G03F7/20 ,  G03F1/24

Abstract: Embodiments described herein comprise extreme ultraviolet (EUV) reticles and methods of forming EUV reticles. In an embodiment, the reticle may comprise a substrate and a mirror layer over the substrate. In an embodiment, the mirror layer comprises a plurality of alternating first mirror layers and second mirror layers. In an embodiment, a phase-shift layer is formed over the mirror layer. In an embodiment, openings for printable features and openings for non-printable features are formed into the phase-shift layer. In an embodiment, the non-printable features have a dimension that is smaller than a dimension of the printable features.

公开(公告)号：US20220148967A1

公开(公告)日：2022-05-12

申请号：US17583078

申请日：2022-01-24

Applicant: INTEL CORPORATION

Inventor： Manish CHANDHOK ,  Richard SCHENKER ,  Tristan TRONIC

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532

Abstract: Integrated circuit (IC) structures, computing devices, and related methods are disclosed. An IC structure includes an interlayer dielectric (ILD), an interconnect, and a liner material separating the interconnect from the ILD. The interconnect includes a first end extending to or into the ILD and a second end opposite the first end. A second portion of the interconnect extending from the second end to a first portion of the interconnect proximate to the first end does not include the liner material thereon. A method of manufacturing an IC structure includes removing an ILD from between interconnects, applying a conformal hermetic liner, applying a carbon hard mask (CHM) between the interconnects, removing a portion of the CHM, removing the conformal hermetic liner to a remaining CHM, and removing the exposed portion of the liner material to the remaining CHM to expose the second portion of the interconnects.

公开(公告)号：US20220310818A1

公开(公告)日：2022-09-29

申请号：US17211751

申请日：2021-03-24

Applicant: Intel Corporation

Inventor： Seung Hoon SUNG ,  Tristan TRONIC ,  Szuya S. LIAO ,  Jack T. KAVALIEROS

IPC: H01L29/49 ,  H01L23/535 ,  H01L27/092 ,  H01L21/28 ,  H01L21/8238

Abstract: Self-aligned gate endcap (SAGE) architectures with reduced or removed caps, and methods of fabricating self-aligned gate endcap (SAGE) architectures with reduced or removed caps, are described. In an example, an integrated circuit structure includes a first gate electrode over a first semiconductor fin. A second gate electrode is over a second semiconductor fin. A gate endcap isolation structure is between the first gate electrode and the second gate electrode, the gate endcap isolation structure having a higher-k dielectric cap layer on a lower-k dielectric wall. A local interconnect is on the first gate electrode, on the higher-k dielectric cap layer, and on the second gate electrode, the local interconnect having a bottommost surface above an uppermost surface of the higher-k dielectric cap layer.

公开(公告)号：US20250022936A1

公开(公告)日：2025-01-16

申请号：US18900116

申请日：2024-09-27

Applicant: Intel Corporation

Inventor： Seung Hoon SUNG ,  Tristan TRONIC ,  Szuya S. LIAO ,  Jack T. KAVALIEROS

IPC: H01L29/49 ,  H01L21/28 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/535 ,  H01L27/088 ,  H01L27/092 ,  H01L29/66

Abstract: Self-aligned gate endcap (SAGE) architectures with reduced or removed caps, and methods of fabricating self-aligned gate endcap (SAGE) architectures with reduced or removed caps, are described. In an example, an integrated circuit structure includes a first gate electrode over a first semiconductor fin. A second gate electrode is over a second semiconductor fin. A gate endcap isolation structure is between the first gate electrode and the second gate electrode, the gate endcap isolation structure having a higher-k dielectric cap layer on a lower-k dielectric wall. A local interconnect is on the first gate electrode, on the higher-k dielectric cap layer, and on the second gate electrode, the local interconnect having a bottommost surface above an uppermost surface of the higher-k dielectric cap layer.

公开(公告)号：US20240038661A1

公开(公告)日：2024-02-01

申请号：US18380466

申请日：2023-10-16

Applicant: Intel Corporation

Inventor： Manish CHANDHOK ,  Richard SCHENKER ,  Tristan TRONIC

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76846 ,  H01L23/53223 ,  H01L23/53266

Abstract: Integrated circuit (IC) structures, computing devices, and related methods are disclosed. An IC structure includes an interlayer dielectric (ILD), an interconnect, and a liner material separating the interconnect from the ILD. The interconnect includes a first end extending to or into the ILD and a second end opposite the first end. A second portion of the interconnect extending from the second end to a first portion of the interconnect proximate to the first end does not include the liner material thereon. A method of manufacturing an IC structure includes removing an ILD from between interconnects, applying a conformal hermetic liner, applying a carbon hard mask (CHM) between the interconnects, removing a portion of the CHM, removing the conformal hermetic liner to a remaining CHM, and removing the exposed portion of the liner material to the remaining CHM to expose the second portion of the interconnects.