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    Real-time statistical analysis on high speed streaming data
    2.
    发明授权
    Real-time statistical analysis on high speed streaming data 有权

    公开(公告)号：US10097600B2

    公开(公告)日：2018-10-09

    申请号：US15215635

    申请日：2016-07-21

    Applicant: International Business Machines Corporation

    Inventor： Suchismita Banerjee ,  Girish G. Kurup ,  Ashutosh Misra ,  Niranjan Vaish

    IPC: H04L29/06 ,  H04L12/26 ,  G06F7/02

    Abstract: A method for analyzing streaming data includes providing a streaming accumulator comprising an addition module and two multiplexers, receiving one or more data streams, continuously calculating a set of basic statistical elements, receiving a request to calculate a set of statistical descriptors, calculating the set of statistical descriptors, and providing the set of statistical descriptors. An apparatus for analyzing streaming data includes a first multiplexer configured to receive a first summation, a second summation, and a current data item, and forward the first summation on cycles 1 and 3, forward the second summation on cycle 4, and forward the current data item on cycle 2, a second multiplexer configured to receiver the second summation, a third summation, and a previous data item, and forward the previous data item on cycles 1 and 3, forward the second summation on cycle 4, and forward the third summation on cycle 2.

    Variable updates of branch prediction states
    4.
    发明授权
    Variable updates of branch prediction states 有权

    公开(公告)号：US09690587B2

    公开(公告)日：2017-06-27

    申请号：US14247813

    申请日：2014-04-08

    Applicant: International Business Machines Corporation

    Inventor： Narasimha R. Adiga ,  James J. Bonanno ,  Ashutosh Misra ,  Anthony Saporito

    IPC: G06F9/38 ,  G06F9/30

    CPC classification number: G06F9/3806 ,  G06F9/30058 ,  G06F9/30061 ,  G06F9/30145 ,  G06F9/3844 ,  G06F9/3848

    Abstract: Embodiments relate to variable branch prediction. An aspect includes determining a branch selection of an execution unit of a processor and determining whether a present prediction state of the state machine correctly predicted the branch selection by the execution unit. The aspect includes determining whether a predetermined condition is met for performing an alternative state transition and, based on determining that the predetermined condition is met, changing the present prediction state of the branch prediction state machine from the one state to another state according to an alternative state transition process based on the branch selection of the execution unit and the determination whether the present prediction state of the state machine correctly predicted the branch selection by the execution unit.

    SCALABLE AND AUTOMATED IDENTIFICATION OF UNOBSERVABILITY CAUSALITY IN LOGIC OPTIMIZATION FLOWS
    5.
    发明申请
    SCALABLE AND AUTOMATED IDENTIFICATION OF UNOBSERVABILITY CAUSALITY IN LOGIC OPTIMIZATION FLOWS 有权

    公开(公告)号：US20170124240A1

    公开(公告)日：2017-05-04

    申请号：US14924898

    申请日：2015-10-28

    Applicant: International Business Machines Corporation

    Inventor： Jason R. Baumgartner ,  Raj K. Gajavelly ,  Ashutosh Misra ,  Pradeep K. Nalla

    IPC: G06F17/50

    CPC classification number: G06F17/505

    Abstract: A method for performing redundancy identification in an integrated circuit design. An optimized gate in a logic circuit is identified. A first netlist with a representation of the logic circuit is generated. An error is induced on the optimized gate. A second netlist is generated from a copy of the first netlist incorporating changes based on the error. Fan-out boundaries of the logic circuit are propagated for the first and second netlists. A redundancy report representing optimization steps performed to obtain the original logic circuit is analyzed to identify which steps are adequate to cause unobservability of the optimized gate. This is done by representing the optimization steps as constraints over the first and second netlists. Responsive to the error becoming undetectable under the constraints derived from the redundancy report, a minimal set of reductions is identified from the first netlist as the reason for unobservability of the optimized gate.

    RAM Based Implementation for Scalable, Reliable High Speed Event Counters
    6.
    发明申请
    RAM Based Implementation for Scalable, Reliable High Speed Event Counters 有权
    基于RAM的实现可扩展，可靠的高速事件计数器

    公开(公告)号：US20130170605A1

    公开(公告)日：2013-07-04

    申请号：US13776687

    申请日：2013-02-25

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Carl Alfred Bender ,  Peter Heiner Hochschild ,  Ashutosh Misra ,  Richard Swetz

    IPC: H03K21/00

    CPC classification number: H03K21/00 ,  G06F11/348 ,  G06F2201/86 ,  G06F2201/88 ,  H03K23/42

    Abstract: There is broadly contemplated herein an arrangement whereby each event source feeds a small dedicated “pre-counter” while an actual count is kept in a 64-bit wide RAM. Such an implementation preferably may involve a state machine that simply sweeps through the pre-counters, in a predetermined fixed order. Preferably, the state machine will access each pre-counter, add the value from the pre-counter to a corresponding RAM location, and then clear the pre-counter. Accordingly, the pre-counters merely have to be wide enough such that even at a maximal event rate, the pre-counter will not be able to wrap (i.e., reach capacity or overflow) before the “sweeper” state machine accesses the pre-counter.

    Abstract translation: 这里广泛考虑了一种布置，其中每个事件源馈送小的专用“预计数器”，而实际计数保持在64位宽的RAM中。 这种实施方式优选地可以包括以预定的固定顺序简单地扫过预先计数器的状态机。 优选地，状态机将访问每个预计数器，将来自预计数器的值添加到相应的RAM位置，然后清除预计数器。 因此，预计数器仅需要足够宽，使得即使在最大事件速率下，在“扫描器”状态机访问预先计数器之前，预计数器将不能包裹（即，达到容量或溢出） 计数器。

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