公开(公告)号：US20250004638A1

公开(公告)日：2025-01-02

申请号：US18217480

申请日：2023-06-30

Applicant: International Business Machines Corporation

Inventor： Bulent Abali ,  Matthias Klein ,  Ashutosh Mishra ,  Girish Gopala Kurup

IPC: G06F3/06

Abstract: A method to handle insufficient on-chip memory capacity in decompressors is disclosed. In one embodiment, such a method includes executing, by a decompressor configured to decompress data, an instruction configured to copy data from a source position within a data stream to a destination position within the data stream. The method determines whether the source position currently resides within an on-chip buffer of the decompressor. In the event the source position does not currently reside within the on-chip buffer of the decompressor, the method writes arbitrary placeholder data to the destination position and adds the instruction to a patch buffer. At a later point in time, the method retrieves the instruction from the patch buffer and executes the instruction by retrieving the data from the source position and overwriting the arbitrary placeholder data at the destination position with the data. A corresponding system and computer program product are also disclosed.

公开(公告)号：US12182627B2

公开(公告)日：2024-12-31

申请号：US17455583

申请日：2021-11-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bulent Abali ,  Alper Buyuktosunoglu ,  Cedric Lichtenau

IPC: G06F9/50 ,  G06F9/38 ,  H04L9/08 ,  H04L9/32

Abstract: Trustworthiness of an accelerator in heterogenous systems is increased. A workload of an application is offloaded to an accelerator for the accelerator to perform the workload. The accelerator is ensured to generate an output of the workload based on offloading the workload. The accelerator is identified as generating an output of the workload based on offloading the workload. Both an input and the output of the workload are ensured to be authentic based on offloading the workload to the accelerator. Both the input and the output of the workload are ensured to be securely transmitted based on offloading the workload to the accelerator.

公开(公告)号：US11847022B2

公开(公告)日：2023-12-19

申请号：US17653825

申请日：2022-03-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bulent Abali ,  Alper Buyuktosunoglu ,  Brian Robert Prasky ,  Deanna Postles Dunn Berger

IPC: G06F11/10 ,  G06F9/30

CPC classification number: G06F11/1044 ,  G06F9/30029 ,  G06F11/1064

Abstract: Computation, placement, and accessing of error correcting codes (ECC) in a computer system data cache enabling partial reads and writes to each line of data in the cache. For storing multiple compressed blocks, received at differing time periods, in a single cache line, the ECC for the first compressed block is stored in the ECC field of the cache and the ECC for the second and subsequently received compressed blocks is appended to the compressed data. Additionally, an auxiliary ECC cache may be constructed for temporarily holding a partial ECC for a partial read/write, and a new ECC for the partial read/write is computed using the partial ECC.

公开(公告)号：US11792303B1

公开(公告)日：2023-10-17

申请号：US17937388

申请日：2022-09-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Rajat Rao ,  Ashutosh Mishra ,  Bulent Abali ,  Alper Buyuktosunoglu

IPC: H04L69/04 ,  H04L67/568

CPC classification number: H04L69/04 ,  H04L67/568

Abstract: Various embodiments are provided herein for compressing data in latency-critical processor links of a computing system in a computing environment. One or more cache lines may be dynamically compressed at a lowest level of a networking stack based on one or more of a plurality of parameters prior to transferring a single-cache line, where the networking stack includes a framer and a data link layer.

公开(公告)号：US11586266B1

公开(公告)日：2023-02-21

申请号：US17443910

申请日：2021-07-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bulent Abali ,  Alper Buyuktosunoglu

IPC: G06F1/26 ,  G06F1/28 ,  G06F1/30 ,  G06F12/0804

Abstract: Data may be transferred from a volatile memory to a non-volatile memory using a persistent power enabled on-chip data processor upon detecting a power loss from a primary power source. The one or more emergency power supplies are attached to the volatile memory, the non-volatile memory, and the persistent power enabled on-chip data processor to assist with the transferring of data.

公开(公告)号：US11336596B2

公开(公告)日：2022-05-17

申请号：US13915547

申请日：2013-06-11

Applicant: International Business Machines Corporation

Inventor： Bulent Abali ,  Michele M. Franceschini ,  Ashish Jagmohan ,  Luis A. Lastras-Montano ,  Livio Soares

IPC: G06F16/00 ,  H04L51/04 ,  H04L51/00 ,  H04L51/222 ,  G06F16/9535 ,  H04L51/52

Abstract: Embodiments relate to personalized low latency communications. A method may include receiving a description of content of a message, receiving recipient data corresponding to at least two possible recipients within a population of possible recipients, and selecting a relevant subpopulation of the population. The selecting may include, for each of the at least two possible recipients, ranking a strength of an indirect relationship between the description and the recipient data. The indirect relationship may be based on the description, the recipient data and at least one additional data source. The selecting may also include, for each of the at least two possible recipients, adding a possible recipient to the relevant subpopulation based on the ranking of the indirect relationship associated with the possible recipient. The method may further include initiating a two-way communication channel between a sender of the message and the relevant subpopulation.

公开(公告)号：US20210150064A1

公开(公告)日：2021-05-20

申请号：US17136332

申请日：2020-12-29

Applicant: International Business Machines Corporation

Inventor： Bulent Abali ,  Mohammad Banikazemi ,  Dan Edward Poff

IPC: G06F21/64

Abstract: An intrusion detection and recovery system includes a copying module that creates a point-in-time copy of a storage level logical unit, the point-in-time copy including a volume copy of the storage level logical unit and signatures of the storage level logical unit, a comparison module that compares at least a portion of the point-in-time copy with a previous copy of the storage level logical unit, a judging module that, based on results of the comparison module, judges if a modification has occurred. A signature of the point-in-time copy is compared with a signature of the previous copy to detect a sign of an intrusion. The signatures of the storage level logical unit include encoded data of files of the storage level logical unit that are monitored in the point-in-time copy.

公开(公告)号：US10929569B2

公开(公告)日：2021-02-23

申请号：US16416732

申请日：2019-05-20

Applicant: International Business Machines Corporation

Inventor： Bulent Abali ,  Mohammad Banikazemi ,  Dan Edward Poff

IPC: G06F21/64 ,  G06F21/56

Abstract: An intrusion detection and recovery system includes a copying module that creates a point-in-time copy of a storage level logical unit, the point-in-time copy including a volume copy of the storage level logical unit and a signature of the storage level logical unit, a comparison module that compares at least a portion of the point-in-time copy with a previous copy of the storage level logical unit, a judging module that, based on results of the comparison module, judges if a modification has occurred. A signature of the point-in-time copy is compared with a signature of the previous copy to detect a sign of an intrusion.

公开(公告)号：US10824953B2

公开(公告)日：2020-11-03

申请号：US14602059

申请日：2015-01-21

Applicant: International Business Machines Corporation

Inventor： Bulent Abali ,  Ganesh Balakrishnan ,  Bartholomew Blaner ,  Peter A. Sandon ,  Jeffrey A. Stuecheli

IPC: G06N5/04 ,  G06F9/30 ,  G06K9/00

Abstract: Various implementations of a method, system, and computer program product for pattern matching using a reconfigurable array processor are disclosed. In one embodiment, a processor array manager of the reconfigurable array processor receives an input data stream for pattern matching and generates a tokenized input data stream from the input data stream. A different portion of the tokenized input data stream is provided to each of a plurality of processing elements of the reconfigurable array processor. Each processing element can compare the received portion of the tokenized input data stream against one or more reference patterns to generate an intermediate result that indicates whether the portion of the tokenized input data stream matches a reference pattern. The processor array manager can combine the intermediate results received from each processing element to yield a final result that indicates whether the input data stream includes a reference pattern.

公开(公告)号：US10817491B2

公开(公告)日：2020-10-27

申请号：US15795248

申请日：2017-10-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bulent Abali ,  Bartholomew Blaner ,  John J. Reilly

IPC: G06F16/22 ,  G06F12/0866 ,  G06F12/02 ,  G06F16/903 ,  H04L29/08

Abstract: Responsive to a data lookup in a buffer triggered for a search string, a processor searches for a selection of pairs from among multiple pairs of a hash table read from at least one address hash of the search string and matching at least one data hash of the search string, each row of the hash table assigned to a separate address hash, each of the pairs comprising a pointer to a location in the buffer and a tag with a previous data hash of a previously buffered string in the buffer. The processor identifies, from among the selection of pairs, at least one separate location in the buffer most frequently pointed to by two or more pointers within the selection of pairs. The processor, responsive to at least one read string from the buffer at the at least one separate location matching at least a substring of the search string, outputs the at least one separate location as the response to the data lookup.