公开(公告)号：US20220382665A1

公开(公告)日：2022-12-01

申请号：US17333640

申请日：2021-05-28

Applicant: International Business Machines Corporation

Inventor： Vitali Sokhin ,  Dean Gilbert Bair ,  Gil Eliezer Shurek ,  Shiri Moran ,  Tom Kolan

IPC: G06F11/36 ,  H04L29/06

Abstract: Embodiments relate to a system, program product, and method for validating a system under test (SUT). The method includes selecting one or more random biases for one or more properties of the one or more API requests. The method also includes transmitting the one or more API requests to the SUT, transmitting an API response from the SUT for each of the one or more API requests, and validating each API response.

公开(公告)号：US09600616B1

公开(公告)日：2017-03-21

申请号：US15264336

申请日：2016-09-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Eli Arbel ,  Erez Barak ,  Bodo Hoppe ,  Udo Krautz ,  Shiri Moran

IPC: G06F9/455 ,  G06F17/50

CPC classification number: G06F17/504 ,  G06F17/5022 ,  G06F17/5036 ,  G06F17/505

Abstract: A computer-implemented method may include retrieving a design netlist with a processor, identifying, via the processor, a logic structure in the design netlist, generating, via the processor, a driver based on the logic structure, applying, via the processor, a simulation and a formal model based on the driver, and testing, via the processor, an output of the simulation and the formal model.

公开(公告)号：US20160154921A1

公开(公告)日：2016-06-02

申请号：US14146770

申请日：2014-01-03

Applicant: International Business Machines Corporation

Inventor： Eli Arbel ,  Pradip Bose ,  Prabhakar Kudva ,  Shiri Moran ,  K. Paul Muller

IPC: G06F17/50

CPC classification number: G06F17/5081

Abstract: A mechanism is provided for validating overall resilience and security characteristics of a sub-component chip design. For each instance of a resiliency template identified as appearing in a design netlist of the sub-component chip design thereby forming one or more identified resiliency sections, a determination is made as to whether an output of the design netlist where an error signal is output interconnects to the one or more identified resiliency sections of the design netlist. Responsive to the one or more identified resiliency sections interconnecting to the output of the design netlist where the error signal is output, one or more identified resiliency sections are marked as being protected by the error signal. An identification of the one or more identified resiliency sections and an identification of the error signal protecting the one or more identified resiliency sections are output to a design team.

Abstract translation: 提供了一种用于验证子组件芯片设计的整体弹性和安全特性的机制。 对于识别为出现在子部件芯片设计的设计网表中的弹性模板的每个实例，从而形成一个或多个所识别的弹性部分，确定输出错误信号的设计网表的输出是否互连 到设计网表的一个或多个标识的弹性部分。 响应于与输出错误信号的设计网表的输出相互连接的一个或多个所识别的弹性部分，一个或多个所识别的弹性部分被标记为受到误差信号的保护。 一个或多个所识别的弹性部分的识别和保护一个或多个所识别的弹性部分的误差信号的识别被输出到设计团队。

公开(公告)号：US11928051B2

公开(公告)日：2024-03-12

申请号：US17806799

申请日：2022-06-14

Applicant: International Business Machines Corporation

Inventor： Vitali Sokhin ,  Gil Eliezer Shurek ,  Shiri Moran ,  Tom Kolan

IPC: G06F11/00 ,  G06F11/36

CPC classification number: G06F11/3688 ,  G06F11/3684 ,  G06F11/3692

Abstract: A system, program product, and method for validating a system under test (SUT). The method includes generating one or more application programming interface (API) requests. The method also includes selecting one or more random biases for one or more properties of the one or more API requests. The method further includes generating a random sample of one or more values from an input domain space, wherein the one or more values are associated with one or more respective fields of the API being requested.

公开(公告)号：US20220382670A1

公开(公告)日：2022-12-01

申请号：US17806799

申请日：2022-06-14

Applicant: International Business Machines Corporation

Inventor： Vitali Sokhin ,  Gil Eliezer Shurek ,  Shiri Moran ,  Tom Kolan

IPC: G06F11/36

Abstract: A system, program product, and method for validating a system under test (SUT). The method includes generating one or more application programming interface (API) requests. The method also includes selecting one or more random biases for one or more properties of the one or more API requests. The method further includes generating a random sample of one or more values from an input domain space, wherein the one or more values are associated with one or more respective fields of the API being requested.

公开(公告)号：US10606971B2

公开(公告)日：2020-03-31

申请号：US15825138

申请日：2017-11-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Erez Barak ,  Shlomit Koyfman ,  Shiri Moran ,  Ido Rozenberg ,  Osher Yifrach

IPC: G06F17/50 ,  G06F11/34 ,  G01R31/3183 ,  G06F13/24

Abstract: Examples of techniques for modifying testing tools are described herein. An example computer-implemented method includes receiving, via a processor, a netlist comprising a complex coverage event that depends on a singular independent signal. The method includes detecting, via the processor, that complex coverage event can be separated into the singular independent signal and a logic state based on a structural logic analysis. The method also includes modifying, via the processor, a testing tool to test the netlist based on the singular independent signal.

公开(公告)号：US09569582B2

公开(公告)日：2017-02-14

申请号：US14146770

申请日：2014-01-03

Applicant: International Business Machines Corporation

Inventor： Eli Arbel ,  Pradip Bose ,  Prabhakar Kudva ,  Shiri Moran ,  K. Paul Muller

IPC: G06F17/50

CPC classification number: G06F17/5081

Abstract: A mechanism is provided for validating overall resilience and security characteristics of a sub-component chip design. For each instance of a resiliency template identified as appearing in a design netlist of the sub-component chip design thereby forming one or more identified resiliency sections, a determination is made as to whether an output of the design netlist where an error signal is output interconnects to the one or more identified resiliency sections of the design netlist. Responsive to the one or more identified resiliency sections interconnecting to the output of the design netlist where the error signal is output, one or more identified resiliency sections are marked as being protected by the error signal. An identification of the one or more identified resiliency sections and an identification of the error signal protecting the one or more identified resiliency sections are output to a design team.

Abstract translation: 提供了一种用于验证子组件芯片设计的整体弹性和安全特性的机制。 对于标识为出现在子部件芯片设计的设计网表中的弹性模板的每个实例，从而形成一个或多个所识别的弹性部分，确定输出错误信号的设计网表的输出是否互连 到设计网表的一个或多个标识的弹性部分。 响应于与输出错误信号的设计网表的输出相互连接的一个或多个所识别的弹性部分，一个或多个所识别的弹性部分被标记为受到误差信号的保护。 一个或多个所识别的弹性部分的识别和保护一个或多个所识别的弹性部分的误差信号的识别被输出到设计团队。

公开(公告)号：US09286426B2

公开(公告)日：2016-03-15

申请号：US14259163

申请日：2014-04-23

Applicant: International Business Machines Corporation

Inventor： Gabor Bobok ,  Shlomit Koyfman ,  Shiri Moran ,  Ziv Nevo ,  Gil Shurek

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5022 ,  G06F17/504

Abstract: A computer-implemented method, apparatus and computer program product for testing a design, the method comprising receiving a design; receiving a description of a scenario, wherein the scenario relates to execution of the design, wherein the scenario is used for verifying the design; translating the scenario to an input for a verification engine, wherein the verification engine is selected from the group consisting of a simulation engine and a formal analysis engine; activating the engine and providing the input to the engine, whereby the engine outputting a result; and displaying the result.

Abstract translation: 一种用于测试设计的计算机实现的方法，装置和计算机程序产品，所述方法包括接收设计; 接收场景的描述，其中所述场景涉及所述设计的执行，其中所述场景用于验证所述设计; 将所述场景转换为用于验证引擎的输入，其中所述验证引擎从由模拟引擎和形式分析引擎组成的组中选择; 启动发动机并向发动机提供输入，由此发动机输出结果; 并显示结果。

公开(公告)号：US12188979B2

公开(公告)日：2025-01-07

申请号：US18326717

申请日：2023-05-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Benjamin Neil Trombley ,  Chung-Lung K. Shum ,  Karl Evan Smock Anderson ,  Bodo Hoppe ,  Erica Stuecheli ,  Shiri Moran ,  Patrick James Meaney ,  Arvind Haran ,  Douglas Balazich

IPC: G01R31/317 ,  G01R31/3181 ,  G01R31/3185

Abstract: Error protection analysis of an integrated circuit includes receiving a design model for the integrated circuit, and a list of error checkers associated with the design model. The design model is traversed from each of the error checkers to group storage cells of the design model into checking groups. The design model is updated to include, for each checking group, a unique group identifier associated with each of the storage cells in the checking group.

公开(公告)号：US11748238B2

公开(公告)日：2023-09-05

申请号：US17333640

申请日：2021-05-28

Applicant: International Business Machines Corporation

Inventor： Vitali Sokhin ,  Dean Gilbert Bair ,  Gil Eliezer Shurek ,  Shiri Moran ,  Tom Kolan

IPC: G06F11/00 ,  G06F11/36 ,  H04L67/133

CPC classification number: G06F11/3684 ,  G06F11/3688 ,  H04L67/133

Abstract: Embodiments relate to a system, program product, and method for validating a system under test (SUT). The method includes selecting one or more random biases for one or more properties of the one or more API requests. The method also includes transmitting the one or more API requests to the SUT, transmitting an API response from the SUT for each of the one or more API requests, and validating each API response.