公开(公告)号：US10157064B2

公开(公告)日：2018-12-18

申请号：US15442810

申请日：2017-02-27

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Lee Evan Eisen ,  Hung Qui Le ,  Jentje Leenstra ,  Jose Eduardo Moreira ,  Bruce Joseph Ronchetti ,  Brian William Thompto ,  Albert James Van Norstrand, Jr.

IPC分类号： G06F9/30 ,  G06F9/45 ,  G06F9/50 ,  G06F15/80 ,  G06F9/38 ,  G06F9/48

摘要： A method of managing instruction execution for multiple instruction streams using a processor core having multiple parallel instruction execution slices. An event is detected indicating that either resource requirement or resource availability for a subsequent instruction of an instruction stream will not be met by the instruction execution slice currently executing the instruction stream. In response to detecting the event, dispatch of at least a portion of the subsequent instruction is made to another instruction execution slice. The event may be a compiler-inserted directive, may be an event detected by logic in the processor core, or may be determined by a thread sequencer. The instruction execution slices may be dynamically reconfigured as between single-instruction-multiple-data (SIMD) instruction execution, ordinary instruction execution, wide instruction execution. When an instruction execution slice is busy processing a current instruction for one of the streams, another slice can be selected to proceed with execution.

公开(公告)号：US10083039B2

公开(公告)日：2018-09-25

申请号：US15883601

申请日：2018-01-30

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Lee Evan Eisen ,  Hung Qui Le ,  Jentje Leenstra ,  Jose Eduardo Moreira ,  Bruce Joseph Ronchetti ,  Brian William Thompto ,  Albert James Van Norstrand, Jr.

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F12/0875 ,  G06F12/0846

CPC分类号： G06F9/3851 ,  G06F9/30145 ,  G06F9/30189 ,  G06F9/3836 ,  G06F9/3887 ,  G06F12/0848 ,  G06F12/0875 ,  G06F2212/1048 ,  G06F2212/282 ,  G06F2212/452 ,  H05K999/99 ,  Y02D10/13

摘要： A processor core having multiple parallel instruction execution slices and coupled to multiple dispatch queues by a dispatch routing network provides flexible and efficient use of internal resources. The configuration of the execution slices is selectable so that capabilities of the processor core can be adjusted according to execution requirements for the instruction streams. Two or more execution slices can be combined as super-slices to handle wider data, wider operands and/or vector operations, according to one or more mode control signal that also serves as a configuration control signal. The mode control signal is also used to partition clusters of the execution slices within the processor core according to whether single-threaded or multi-threaded operation is selected, and additionally according to a number of hardware threads that are active.

公开(公告)号：US20150324206A1

公开(公告)日：2015-11-12

申请号：US14300563

申请日：2014-06-10

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Lee Evan Eisen ,  Hung Qui Le ,  Jentje Leenstra ,  Jose Eduardo Moreira ,  Bruce Joseph Ronchetti ,  Brian William Thompto ,  Albert James Van Norstrand, JR.

IPC分类号： G06F9/38

CPC分类号： G06F9/38 ,  G06F9/30149 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3867 ,  G06F9/3873 ,  G06F9/3887 ,  G06F9/4881 ,  G06F9/505 ,  G06F9/5066 ,  G06F9/5083

摘要： A method of operation of a processor core having multiple parallel instruction execution slices and coupled to multiple dispatch queues coupled by a dispatch routing network provides flexible and efficient use of internal resources. The dispatch routing network is controlled to dynamically vary the relationship between the slices and instruction streams according to execution requirements for the instruction streams and the availability of resources in the instruction execution slices. The instruction execution slices may be dynamically reconfigured as between single-instruction-multiple-data (SIMD) instruction execution and ordinary instruction execution on a per-instruction basis. Instructions having an operand width greater than the width of a single instruction execution slice may be processed by multiple instruction execution slices configured to act in concert for the particular instructions. When an instruction execution slice is busy processing a current instruction for one of the streams, another slice can be selected to proceed with execution.

摘要翻译： 具有多个并行指令执行片并且耦合到由调度路由网络耦合的多个调度队列的处理器核心的操作方法提供了内部资源的灵活和有效的使用。 根据指令流的执行要求和指令执行片中的资源的可用性，控制调度路由网络动态地改变片和指令流之间的关系。 可以在单指令多数据（SIMD）指令执行和基于每个指令的普通指令执行之间动态地重新配置指令执行片。 具有大于单个指令执行片段的宽度的操作数宽度的指令可以被配置为为特定指令一致地起作用的多个指令执行片段来处理。 当指令执行片正忙于处理其中一个流的当前指令时，可以选择另一个片段来继续执行。

公开(公告)号：US10983800B2

公开(公告)日：2021-04-20

申请号：US16001333

申请日：2018-06-06

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Lee Evan Eisen ,  Hung Qui Le ,  Jentje Leenstra ,  Jose Eduardo Moreira ,  Bruce Joseph Ronchetti ,  Brian William Thompto ,  Albert James Van Norstrand, Jr.

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F12/0875 ,  G06F12/0846

摘要： A processor core having multiple parallel instruction execution slices and coupled to multiple dispatch queues provides flexible and efficient use of internal resources. The configuration of the execution slices is selectable so that capabilities of the processor core can be adjusted according to execution requirements for the instruction streams. A plurality of load-store slices coupled to the execution slices provides access to a plurality of cache slices that partition the lowest level of cache memory among the load-store slices.

公开(公告)号：US20180285118A1

公开(公告)日：2018-10-04

申请号：US16001333

申请日：2018-06-06

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Lee Evan Eisen ,  Hung Qui Le ,  Jentje Leenstra ,  Jose Eduardo Moreira ,  Bruce Joseph Ronchetti ,  Brian William Thompto ,  Albert James Van Norstrand, JR.

IPC分类号： G06F9/38 ,  G06F12/0875 ,  G06F9/30 ,  G06F12/0846

摘要： A processor core having multiple parallel instruction execution slices and coupled to multiple dispatch queues provides flexible and efficient use of internal resources. The configuration of the execution slices is selectable so that capabilities of the processor core can be adjusted according to execution requirements for the instruction streams. A plurality of load-store slices coupled to the execution slices provides access to a plurality of cache slices that partition the lowest level of cache memory among the load-store slices.

公开(公告)号：US09690586B2

公开(公告)日：2017-06-27

申请号：US14302589

申请日：2014-06-12

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Lee Evan Eisen ,  Hung Qui Le ,  Jentje Leenstra ,  Jose Eduardo Moreira ,  Bruce Joseph Ronchetti ,  Brian William Thompto ,  Albert James Van Norstrand, Jr.

IPC分类号： G06F9/38 ,  G06F9/46 ,  G06F15/80 ,  G06F9/30

CPC分类号： G06F9/3851 ,  G06F9/30149 ,  G06F9/38 ,  G06F9/3836 ,  G06F9/3867 ,  G06F9/3887 ,  G06F9/4843 ,  G06F9/4881 ,  G06F9/5027 ,  G06F9/5083 ,  G06F15/8007

摘要： A method of managing instruction execution for multiple instruction streams using a processor core having multiple parallel instruction execution slices provides instruction processing flexibility. An event is detected indicating that either resource requirement or resource availability for a subsequent instruction of an instruction stream will not be met by the instruction execution slice currently executing the instruction stream. In response to detecting the event, dispatch of at least a portion of the subsequent instruction is made to another instruction execution slice. The event may be a compiler-inserted directive, may be an event detected by logic in the processor core, or may be determined by a thread sequencer. The execution slices may be dynamically reconfigured as between single-instruction-multiple-data (SIMD) instruction execution, ordinary instruction execution, wide instruction execution. When an execution slice is busy processing a current instruction for one of the streams, another slice can be selected to proceed with execution.

公开(公告)号：US09690585B2

公开(公告)日：2017-06-27

申请号：US14300563

申请日：2014-06-10

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Lee Evan Eisen ,  Hung Qui Le ,  Jentje Leenstra ,  Jose Eduardo Moreira ,  Bruce Joseph Ronchetti ,  Brian William Thompto ,  Albert James Van Norstrand, Jr.

IPC分类号： G06F9/38 ,  G06F9/46 ,  G06F15/80 ,  G06F9/30 ,  G06F9/50 ,  G06F9/48

CPC分类号： G06F9/38 ,  G06F9/30149 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3867 ,  G06F9/3873 ,  G06F9/3887 ,  G06F9/4881 ,  G06F9/505 ,  G06F9/5066 ,  G06F9/5083

摘要： A method of operation of a processor core having multiple parallel instruction execution slices and coupled to multiple dispatch queues coupled by a dispatch routing network provides flexible and efficient use of internal resources. The dispatch routing network is controlled to dynamically vary the relationship between the slices and instruction streams according to execution requirements for the instruction streams and the availability of resources in the instruction execution slices. The instruction execution slices may be dynamically reconfigured as between single-instruction-multiple-data (SIMD) instruction execution and ordinary instruction execution on a per-instruction basis. Instructions having an operand width greater than the width of a single instruction execution slice may be processed by multiple instruction execution slices configured to act in concert for the particular instructions. When an instruction execution slice is busy processing a current instruction for one of the streams, another slice can be selected to proceed with execution.

公开(公告)号：US09665372B2

公开(公告)日：2017-05-30

申请号：US14274927

申请日：2014-05-12

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Lee Evan Eisen ,  Hung Qui Le ,  Jentje Leenstra ,  Jose Eduardo Moreira ,  Bruce Joseph Ronchetti ,  Brian William Thompto ,  Albert James Van Norstrand, Jr.

IPC分类号： G06F9/38 ,  G06F9/46 ,  G06F15/80 ,  G06F9/30 ,  G06F9/50 ,  G06F9/48

CPC分类号： G06F9/38 ,  G06F9/30149 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3867 ,  G06F9/3873 ,  G06F9/3887 ,  G06F9/4881 ,  G06F9/505 ,  G06F9/5066 ,  G06F9/5083

摘要： A processor core having multiple parallel instruction execution slices and coupled to multiple dispatch queues by a dispatch routing network provides flexible and efficient use of internal resources. The dispatch routing network is controlled to dynamically vary the relationship between the slices and instruction streams according to execution requirements for the instruction streams and the availability of resources in the instruction execution slices. The instruction execution slices may be dynamically reconfigured as between single-instruction-multiple-data (SIMD) instruction execution and ordinary instruction execution on a per-instruction basis, permitting the mixture of those instruction types. Instructions having an operand width greater than the width of a single instruction execution slice may be processed by multiple instruction execution slices configured to act in concert for the particular instructions. When an instruction execution slice is busy processing a current instruction for one of the streams, another slice can be selected to proceed with execution.

公开(公告)号：US20150324205A1

公开(公告)日：2015-11-12

申请号：US14274942

申请日：2014-05-12

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Lee Evan Eisen ,  Hung Qui Le ,  Jentje Leenstra ,  Jose Eduardo Moreira ,  Bruce Joseph Ronchetti ,  Brian William Thompto ,  Albert James Van Norstrand, JR.

IPC分类号： G06F9/38

CPC分类号： G06F9/3851 ,  G06F9/30149 ,  G06F9/38 ,  G06F9/3836 ,  G06F9/3867 ,  G06F9/3887 ,  G06F9/4843 ,  G06F9/4881 ,  G06F9/5027 ,  G06F9/5083 ,  G06F15/8007

摘要： Techniques for managing instruction execution for multiple instruction streams using a processor core having multiple parallel instruction execution slices provide flexibility in execution of program instructions by a processor core. An event is detected indicating that either resource requirement or resource availability will not be met by the execution slice currently executing the instruction stream. In response to detecting the event, dispatch of at least a portion of the subsequent instruction is made to another instruction execution slice. The event may be a compiler-inserted directive, may be an event detected by logic in the processor core, or may be determined by a thread sequencer. The instruction execution slices may be dynamically reconfigured as between single-instruction-multiple-data (SIMD) instruction execution, ordinary instruction execution, wide instruction execution. When an instruction execution slice is busy processing a current instruction for one of the streams, another slice can be selected to proceed with execution.

摘要翻译： 用于使用具有多个并行指令执行片的处理器核来管理多个指令流的指令执行的技术提供了由处理器核心执行程序指令的灵活性。 检测到指示资源需求或资源可用性不会被当前正在执行指令流的执行片段满足的事件。 响应于检测到事件，对后续指令的至少一部分进行调度到另一个指令执行片。 事件可以是编译器插入的指令，可以是由处理器核心中的逻辑检测到的事件，或者可以由线程序列器确定。 指令执行片可以在单指令多数据（SIMD）指令执行，普通指令执行，宽指令执行之间动态地重新配置。 当指令执行片正忙于处理其中一个流的当前指令时，可以选择另一个片段来继续执行。

公开(公告)号：US20180150300A1

公开(公告)日：2018-05-31

申请号：US15883601

申请日：2018-01-30

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Lee Evan Eisen ,  Hung Qui Le ,  Jentje Leenstra ,  Jose Eduardo Moreira ,  Bruce Joseph Ronchetti ,  Brian William Thompto ,  Albert James Van Norstrand, JR.

IPC分类号： G06F9/38 ,  G06F12/0875 ,  G06F12/0846 ,  G06F9/30

CPC分类号： G06F9/3851 ,  G06F9/30145 ,  G06F9/30189 ,  G06F9/3836 ,  G06F9/3887 ,  G06F12/0848 ,  G06F12/0875 ,  G06F2212/1048 ,  G06F2212/282 ,  G06F2212/452

摘要： A processor core having multiple parallel instruction execution slices and coupled to multiple dispatch queues by a dispatch routing network provides flexible and efficient use of internal resources. The configuration of the execution slices is selectable so that capabilities of the processor core can be adjusted according to execution requirements for the instruction streams. Two or more execution slices can be combined as super-slices to handle wider data, wider operands and/or vector operations, according to one or more mode control signal that also serves as a configuration control signal. The mode control signal is also used to partition clusters of the execution slices within the processor core according to whether single-threaded or multi-threaded operation is selected, and additionally according to a number of hardware threads that are active.