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公开(公告)号：US10685106B2
公开(公告)日：2020-06-16
申请号：US15917619
申请日：2018-03-10
发明人： Richard H. Boivie , Jonathan D. Bradbury , William E. Hall , Guerney D. H. Hunt , Jentje Leenstra , Jeb R. Linton , James A. O'Connor, Jr. , Elaine R. Palmer , Dimitrios Pendarakis
摘要： A secure cloud computing environment protects the confidentiality of application code from a customer while simultaneously protecting the confidentiality of a customer's data from intentional or inadvertent leaks by the application code. This result is accomplished without the need to trust the application code and without requiring human surveillance or intervention. A client secure virtual machine (SVM) is accessible by a client who supplies commands, operand data and application data. An appliance SVM has the application code loaded therein and includes an application program interface that accesses a memory area shared by both SVMs. All access to the appliance SVM is initially revoked by an ultravisor, except for the shared memory. The appliance SVM processes the commands without ever saving any persistent state of the application data. The ultravisor manages an SVM by maintaining exclusive control over a device tree used by the operating system of the SVM.
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公开(公告)号：US20200073668A1
公开(公告)日：2020-03-05
申请号：US16676763
申请日：2019-11-07
发明人： Sam G. Chu , Markus Kaltenbach , Hung Q. Le , Jentje Leenstra , Jose E. Moreira , Dung Q. Nguyen , Brian W. Thompto
摘要： Embodiments of the present invention provide systems and methods for mapping the architected state of one or more threads to a set of distributed physical register files to enable independent execution of one or more threads in a multiple slice processor. In one embodiment, a system is disclosed including a plurality of dispatch queues which receive instructions from one or more threads and an even number of parallel execution slices, each parallel execution slice containing a register file. A routing network directs an output from the dispatch queues to the parallel execution slices and the parallel execution slices independently execute the one or more threads.
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公开(公告)号：US10387686B2
公开(公告)日：2019-08-20
申请号：US15661048
申请日：2017-07-27
发明人： Richard H. Boivie , Bradly G. Frey , William E. Hall , Benjamin Herrenschmidt , Guerney D. H. Hunt , Jentje Leenstra , Paul Mackerras , Cathy May , Albert J. Van Norstrand, Jr.
摘要： Hardware based isolation for secure execution of virtual machines (VMs). At least one virtual machine is executed via operation of a hypervisor and an ultravisor. A first memory component is configured for access by the hypervisor and the ultravisor, and a second memory component is configured for access by the ultravisor and not by the hypervisor. A first mode of operation is operated, such that the virtual machine is executed using the hypervisor, wherein the first memory component is accessible to the virtual machine and the second memory component is not accessible to the virtual machine. A second mode of operation is operated, such that the virtual machine is executed using the ultravisor, wherein the first memory component and the second memory component are accessible to the virtual machine, thereby executing application code and operating system code using the second memory component without code changes.
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4.发明授权公开(公告)号：US10387150B2
公开(公告)日：2019-08-20
申请号：US14748550
申请日：2015-06-24
IPC分类号： G06F9/30
摘要： A machine instruction to find a condition location within registers, such as vector registers. The machine instruction has associated therewith a register to be examined and a result location. The register includes a plurality of elements. In execution, the machine instruction counts a number of contiguous elements of the plurality of elements of the register having a particular value in a selected location within the contiguous elements. Other locations within the contiguous elements are ignored for the counting. The counting provides a count placed in the result location.
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公开(公告)号：US10223196B2
公开(公告)日：2019-03-05
申请号：US15805301
申请日：2017-11-07
发明人： Brian D. Barrick , James W. Bishop , Maarten J. Boersma , Marcy E. Byers , Sundeep Chadha , Jentje Leenstra , Dung Q. Nguyen , David R. Terry
摘要： Techniques for error correction in a processor include detecting an error in first data stored in a register. The method also includes generating an instruction to read the first data stored in the register, where the register is both a source register and a destination register of the instruction. The method further includes transmitting the first data to an execution unit, where the first data bypasses an issue queue. The method also includes decoding the instruction and correcting the error to generate corrected data and writing the corrected data to the destination register.
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6.发明申请公开(公告)号：US20180150300A1
公开(公告)日：2018-05-31
申请号：US15883601
申请日：2018-01-30
发明人： Lee Evan Eisen , Hung Qui Le , Jentje Leenstra , Jose Eduardo Moreira , Bruce Joseph Ronchetti , Brian William Thompto , Albert James Van Norstrand, JR.
IPC分类号： G06F9/38 , G06F12/0875 , G06F12/0846 , G06F9/30
CPC分类号： G06F9/3851 , G06F9/30145 , G06F9/30189 , G06F9/3836 , G06F9/3887 , G06F12/0848 , G06F12/0875 , G06F2212/1048 , G06F2212/282 , G06F2212/452
摘要： A processor core having multiple parallel instruction execution slices and coupled to multiple dispatch queues by a dispatch routing network provides flexible and efficient use of internal resources. The configuration of the execution slices is selectable so that capabilities of the processor core can be adjusted according to execution requirements for the instruction streams. Two or more execution slices can be combined as super-slices to handle wider data, wider operands and/or vector operations, according to one or more mode control signal that also serves as a configuration control signal. The mode control signal is also used to partition clusters of the execution slices within the processor core according to whether single-threaded or multi-threaded operation is selected, and additionally according to a number of hardware threads that are active.
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公开(公告)号：US09971602B2
公开(公告)日：2018-05-15
申请号：US14723940
申请日：2015-05-28
发明人： Lee Evan Eisen , Hung Qui Le , Jentje Leenstra , Jose Eduardo Moreira , Bruce Joseph Ronchetti , Brian William Thompto , Albert James Van Norstrand, Jr.
IPC分类号： G06F9/38 , G06F9/30 , G06F12/0846 , G06F12/0875
CPC分类号： G06F9/3851 , G06F9/30145 , G06F9/30189 , G06F9/3836 , G06F9/3887 , G06F12/0848 , G06F12/0875 , G06F2212/1048 , G06F2212/282 , G06F2212/452
摘要： A method of operating a processor core having multiple parallel instruction execution slices and coupled to multiple dispatch queues by a dispatch routing network provides flexible and efficient use of internal resources. The configuration of the execution slices is selectable so that capabilities of the processor core can be adjusted according to execution requirements for the instruction streams. Two or more execution slices can be combined as super-slices to handle wider data, wider operands and/or vector operations, according to one or more mode control signal that also serves as a configuration control signal. The mode control signal is also used to partition clusters of the execution slices within the processor core according to whether single-threaded or multi-threaded operation is selected, and additionally according to a number of hardware threads that are active.
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公开(公告)号：US20160202989A1
公开(公告)日：2016-07-14
申请号：US14594716
申请日：2015-01-12
发明人： Lee Evan Eisen , Hung Qui Le , Jentje Leenstra , Jose Eduardo Moreira , Bruce Joseph Ronchetti , Brian William Thompto , Albert James Van Norstrand, JR.
CPC分类号： G06F9/3851 , G06F9/30145 , G06F9/30189 , G06F9/3836 , G06F9/3887 , G06F12/0848 , G06F12/0875 , G06F2212/1048 , G06F2212/282 , G06F2212/452
摘要： A processor core having multiple parallel instruction execution slices and coupled to multiple dispatch queues by a dispatch routing network provides flexible and efficient use of internal resources. The configuration of the execution slices is selectable so that capabilities of the processor core can be adjusted according to execution requirements for the instruction streams. Two or more execution slices can be combined as super-slices to handle wider data, wider operands and/or vector operations, according to one or more mode control signal that also serves as a configuration control signal. The mode control signal is also used to partition clusters of the execution slices within the processor core according to whether single-threaded or multi-threaded operation is selected, and additionally according to a number of hardware threads that are active.
摘要翻译： 具有多个并行指令执行片并通过调度路由网络耦合到多个调度队列的处理器核心提供内部资源的灵活和有效的使用。 执行片的配置是可选择的，使得可以根据指令流的执行要求来调整处理器核的能力。 根据一个或多个也用作配置控制信号的模式控制信号，可以将两个或更多个执行片组合成超片以处理较宽的数据，较宽的操作数和/或矢量操作。 模式控制信号还用于根据是否选择单线程或多线程操作以及另外根据活动的多个硬件线程来分配处理器核心内的执行片段的簇。
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公开(公告)号：US20160070574A1
公开(公告)日：2016-03-10
申请号：US14480680
申请日：2014-09-09
CPC分类号： G06F9/30105 , G06F9/30112 , G06F9/3012 , G06F9/30138 , G06F9/3828 , G06F9/3836 , G06F9/3887 , G06F9/3891
摘要： A processor core includes even and odd execution slices each having a register file. The slices are each configured to perform operations specified in a first set of instructions on data from its respective register file, and together configured to perform operations specified in a second set of instructions on data stored across both register files. During utilization, the processor receives a first instruction of the first set specifying an operation, a target register, and a source register. Next, a second instruction upon which content of the source register depends is identified as being of the second set. In response, the first instruction is dispatched to the even slice. In accordance with the operation specified in the first instruction, the even slice uses content of the source register in its register file to produce a result. Copies of the result are written to the target register in both register files.
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公开(公告)号：US20150324204A1
公开(公告)日：2015-11-12
申请号：US14274927
申请日：2014-05-12
发明人： Lee Evan Eisen , Hung Qui Le , Jentje Leenstra , Jose Eduardo Moreira , Bruce Joseph Ronchetti , Brian William Thompto , Albert James Van Norstrand, JR.
IPC分类号： G06F9/38
CPC分类号： G06F9/38 , G06F9/30149 , G06F9/3836 , G06F9/3851 , G06F9/3867 , G06F9/3873 , G06F9/3887 , G06F9/4881 , G06F9/505 , G06F9/5066 , G06F9/5083
摘要： A processor core having multiple parallel instruction execution slices and coupled to multiple dispatch queues by a dispatch routing network provides flexible and efficient use of internal resources. The dispatch routing network is controlled to dynamically vary the relationship between the slices and instruction streams according to execution requirements for the instruction streams and the availability of resources in the instruction execution slices. The instruction execution slices may be dynamically reconfigured as between single-instruction-multiple-data (SIMD) instruction execution and ordinary instruction execution on a per-instruction basis, permitting the mixture of those instruction types. Instructions having an operand width greater than the width of a single instruction execution slice may be processed by multiple instruction execution slices configured to act in concert for the particular instructions. When an instruction execution slice is busy processing a current instruction for one of the streams, another slice can be selected to proceed with execution.
摘要翻译： 具有多个并行指令执行片并通过调度路由网络耦合到多个调度队列的处理器核心提供内部资源的灵活和有效的使用。 根据指令流的执行要求和指令执行片中的资源的可用性，控制调度路由网络动态地改变片和指令流之间的关系。 可以在单指令多数据（SIMD）指令执行和基于每个指令的普通指令执行之间动态地重新配置指令执行片，允许这些指令类型的混合。 具有大于单个指令执行片段的宽度的操作数宽度的指令可以被配置为为特定指令一致地起作用的多个指令执行片段来处理。 当指令执行片正忙于处理其中一个流的当前指令时，可以选择另一个片段来继续执行。
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