公开(公告)号：US20230315627A1

公开(公告)日：2023-10-05

申请号：US17696089

申请日：2022-03-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bulent Abali ,  Alper Buyuktosunoglu ,  Brian Robert Prasky ,  Deanna Postles Dunn Berger

IPC: G06F12/12 ,  G06F12/0802

CPC classification number: G06F12/0802 ,  G06F12/12 ,  G06F2212/60

Abstract: A central processing unit (CPU) system including a CPU core can include an adaptive cache compressor, which is capable of monitoring a miss profile of a cache. The adaptive cache compressor can compare the miss profile to a miss threshold. Based on this comparison, the adaptive cache compressor can determine whether to enable compression of the cache.

公开(公告)号：US20230053733A1

公开(公告)日：2023-02-23

申请号：US17406452

申请日：2021-08-19

Applicant: International Business Machines Corporation

Inventor： Adam Benjamin Collura ,  JAMES BONANNO ,  Brian Robert Prasky

IPC: G06F16/2453 ,  G06F16/21

Abstract: Embodiments are provided for using metadata presence information to determine when to access a higher-level metadata table. It is determined that an incomplete hit occurred for a line of metadata in a lower-level structure of a processor, the lower-level structure being coupled to a higher-level structure in a hierarchy. It is determined that metadata presence information in a metadata presence table is a match to the line of metadata from the lower-level structure. Responsive to determining the match, it is determined to avoid accessing the higher-level structure of the processor.

公开(公告)号：US11573899B1

公开(公告)日：2023-02-07

申请号：US17451763

申请日：2021-10-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bulent Abali ,  Alper Buyuktosunoglu ,  Brian Robert Prasky ,  Deanna Postles Dunn Berger

IPC: G06F12/0846

Abstract: Low latency in a non-uniform cache access (“NUCA”) cache in a computing environment is provided. A first compressed cache line is interleaved with a second compressed cache line into a single cache line of the NUCA cache, where data of the first compressed cache line is stored in one or more even sectors in the single cache line and stored in zero or more odd sectors in the single cache line after the data fills the one or more even sectors, and data of the second compressed cache line is stored in the one or more odd sectors in the single cache line and stored in zero or more even sectors in the single cache line after the data fills the one or more odd sectors.

公开(公告)号：US11556474B1

公开(公告)日：2023-01-17

申请号：US17406438

申请日：2021-08-19

Applicant: International Business Machines Corporation

Inventor： James Bonanno ,  Adam Benjamin Collura ,  Edward Thomas Malley ,  Brian Robert Prasky

IPC: G06F12/0855 ,  G06F12/0897 ,  G06F9/38

Abstract: Embodiments are provided for an integrated semi-inclusive hierarchical metadata predictor. A hit in a second-level structure is determined, the hit being associated with a line of metadata in the second-level structure. Responsive to determining that a victim line of metadata in a first-level structure meets at least one condition, the victim line of metadata is stored in the second-level structure. The line of metadata from the second-level structure is stored in a first-level structure to be utilized to facilitate performance of a processor, the line of metadata from the second-level structure including entries for a plurality of instructions.

公开(公告)号：US20230305850A1

公开(公告)日：2023-09-28

申请号：US17703063

申请日：2022-03-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Brian Robert Prasky ,  James Bonanno ,  Adam Benjamin Collura ,  Edward Thomas Malley ,  Deepankar Bhattacharjee

IPC: G06F9/38

CPC classification number: G06F9/3806 ,  G06F9/3867

Abstract: A method of branch prediction in a processor includes: obtaining, by the processor, a branch instruction for which a direction of a branch is to be predicted; generating, by the processor, an index based on an instruction address, a global path vector (GPV), and a counter; selecting, by the processor, an entry from a data structure using the index; and predicting, by the processor, the direction of the branch using information included in the selected entry. The method may include modifying a tag in the selected entry based at least in part on another GPV.

公开(公告)号：US11663126B1

公开(公告)日：2023-05-30

申请号：US17678179

申请日：2022-02-23

Applicant: International Business Machines Corporation

Inventor： James Bonanno ,  Brian Robert Prasky ,  Adam Benjamin Collura ,  Edward Thomas Malley ,  James Raymond Cuffney ,  Dominic Ditomaso

IPC: G06F12/08 ,  G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/60

Abstract: Embodiments include storing return addresses for a branch-target-buffer. Aspects include receiving a first instruction and based on a determination that the first instruction is a branch instruction and potentially a call, storing a return address associated with the branch instruction in a prediction return address table, wherein the prediction return address table includes an entry that corresponds to an index value that is created based on a target address of the first instruction, and wherein the entry includes the return address that is created based on an address of a sequential instruction of the first instruction. Aspects also include receiving a second instruction and based on a determination that the second instruction is predicted to be a return instruction with a predicted return address table index value from the branch-target-buffer, using the index value to select the return address to predict as the target address.

公开(公告)号：US11182165B2

公开(公告)日：2021-11-23

申请号：US16194452

申请日：2018-11-19

Applicant: International Business Machines Corporation

Inventor： James Bonanno ,  Daniel Lipetz ,  Brian Robert Prasky ,  Anthony Saporito ,  Adam Collura ,  Steven J. Hnatko

IPC: G06F9/38 ,  G06F9/355 ,  G06F9/30

Abstract: A system includes a branch predictor and a processing circuit configured to perform a plurality of operations including storing a skip-over offset value in the branch predictor. The skip-over offset value defines a number of search addresses of the branch predictor to be skipped. The operations further include searching the branch predictor for a branch prediction. Responsive to finding the branch prediction, the searching of the branch predictor is re-indexed based on the skip-over offset value associated with the branch prediction.

公开(公告)号：US11847022B2

公开(公告)日：2023-12-19

申请号：US17653825

申请日：2022-03-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bulent Abali ,  Alper Buyuktosunoglu ,  Brian Robert Prasky ,  Deanna Postles Dunn Berger

IPC: G06F11/10 ,  G06F9/30

CPC classification number: G06F11/1044 ,  G06F9/30029 ,  G06F11/1064

Abstract: Computation, placement, and accessing of error correcting codes (ECC) in a computer system data cache enabling partial reads and writes to each line of data in the cache. For storing multiple compressed blocks, received at differing time periods, in a single cache line, the ECC for the first compressed block is stored in the ECC field of the cache and the ECC for the second and subsequently received compressed blocks is appended to the compressed data. Additionally, an auxiliary ECC cache may be constructed for temporarily holding a partial ECC for a partial read/write, and a new ECC for the partial read/write is computed using the partial ECC.

公开(公告)号：US11782919B2

公开(公告)日：2023-10-10

申请号：US17406452

申请日：2021-08-19

Applicant: International Business Machines Corporation

Inventor： Adam Benjamin Collura ,  James Bonanno ,  Brian Robert Prasky

IPC: G06F16/24 ,  G06F16/2453 ,  G06F16/21

CPC classification number: G06F16/2453 ,  G06F16/211

Abstract: Embodiments are provided for using metadata presence information to determine when to access a higher-level metadata table. It is determined that an incomplete hit occurred for a line of metadata in a lower-level structure of a processor, the lower-level structure being coupled to a higher-level structure in a hierarchy. It is determined that metadata presence information in a metadata presence table is a match to the line of metadata from the lower-level structure. Responsive to determining the match, it is determined to avoid accessing the higher-level structure of the processor.

公开(公告)号：US11163573B2

公开(公告)日：2021-11-02

申请号：US16274710

申请日：2019-02-13

Applicant: International Business Machines Corporation

Inventor： James Bonanno ,  Varnika Atmakuri ,  Adam Collura ,  Brian Robert Prasky ,  Anthony Saporito ,  Suman Amugothu

IPC: G06F9/30 ,  G06F9/38

Abstract: A system includes a hierarchical metadata predictor and a processing circuit. The hierarchical metadata predictor includes a first-level metadata predictor and a second-level metadata predictor. The processing circuit is configured to perform a plurality of operations including storing new or updated metadata into the first-level metadata predictor and searching the first-level metadata predictor for a metadata prediction. Responsive to finding the metadata prediction in the first-level metadata predictor, the metadata prediction is output corresponding to an entry of the first-level metadata predictor that is a hit. One or more entries of the first-level metadata predictor that are non-hits are periodically written to the second-level metadata predictor. The first-level metadata predictor is updated based on locating the metadata prediction in the second-level metadata predictor.