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公开(公告)号：US20210225845A1
公开(公告)日：2021-07-22
申请号：US17224258
申请日：2021-04-07
IPC分类号： H01L27/108 , G11C11/404
摘要： The invention relates to a capacitorless DRAM cell, the cell comprising a heterostructure, a gate structure adjoining the heterostructure in a first direction, a drain structure adjoining the heterostructure in a second direction perpendicular to the first direction, and a source structure adjoining the heterostructure in the direction opposite the second direction, the heterostructure comprising one or more semiconducting channel layers and one or more electrically insulating barrier layers, the channel layers and the barrier layers being alternatingly stacked in the first direction.
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公开(公告)号：US11031402B1
公开(公告)日：2021-06-08
申请号：US16703916
申请日：2019-12-05
IPC分类号： H01L27/108 , G11C11/404 , G11C11/401
摘要： The invention relates to a capacitorless DRAM cell, the cell comprising a heterostructure, a gate structure adjoining the heterostructure in a first direction, a drain structure adjoining the heterostructure in a second direction perpendicular to the first direction, and a source structure adjoining the heterostructure in the direction opposite the second direction, the heterostructure comprising one or more semiconducting channel layers and one or more electrically insulating barrier layers, the channel layers and the barrier layers being alternatingly stacked in the first direction.
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公开(公告)号：US20210143282A1
公开(公告)日：2021-05-13
申请号：US16681225
申请日：2019-11-12
发明人： Clarissa Convertino , Cezar Bogdan Zota , Kirsten Emilie Moselund , Lukas Czornomaz , Davide Cutaia
IPC分类号： H01L29/786 , H01L29/66 , H01L29/40 , H01L29/08
摘要： The present disclosure relates to a method for fabricating an FET structure. The method includes forming on a substrate a first semiconductor structure and an insulator structure covering the first semiconductor structure with a first insulator layer, forming on the first insulator layer a sacrificial layer extending to a reference plane, forming a second insulator layer on the reference plane, forming a first cavity through the second insulator layer, the sacrificial layer and the first insulator layer, thus exposing a surface of the first semiconductor structure, filling the first cavity with a second semiconductor structure extending from the surface at least up to the first reference plane, forming a third semiconductor structure on the second semiconductor structure, selectively removing the sacrificial layer, thus forming a second cavity, and filling the second cavity with a gate structure.
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公开(公告)号：US10810506B1
公开(公告)日：2020-10-20
申请号：US16806078
申请日：2020-03-02
发明人： Cezar Bogdan Zota , Lukas Czornomaz
IPC分类号： G06N10/00 , H03K19/195 , G11C11/44 , H03K3/38 , G11C13/00
摘要： A quantum processing apparatus comprises control electronics, a switching unit, a bias line, and N electronic circuits. Both the switching unit and the bias line are connected to the control electronics. The N circuits comprise N respective, non-volatilely tunable resistors and N respective frequency-tunable, solid-state qubits. The control electronics are configured to individually tune the resistors via the switching unit, in a configuration mode of the apparatus; and apply a voltage bias to the electronic circuits via the bias line, in an operation mode of the apparatus. The electronic circuits are configured to passively apply respective bias signals to the qubits, wherein such bias signals are impacted by the resistors, in response to the voltage bias applied via the bias line, to operate the qubits at respective frequencies determined according to the respective bias signals.
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公开(公告)号：US20230139805A1
公开(公告)日：2023-05-04
申请号：US17453499
申请日：2021-11-04
发明人： Thomas Morf , Cezar Bogdan Zota , Peter Mueller , Pier Andrea Francese , Marcel A. Kossel , Matthias Braendli , Mridula Prathapan
摘要： The invention relates to a control unit for controlling a data transfer between a classical processor and a quantum processor with a plurality of qubits. The control unit comprises a plurality of control and read-out circuits configured for controlling and reading out the plurality of qubits. Each of the control and read-out circuits is assigned to one or more of the qubits. A controlling of the quantum processor by the control unit comprises selectively powering on a subset of the control and read-out circuits during an instruction cycle, while ensuring that the remaining control and read-out circuits are powered off during the instruction cycle. The powered-on subset of control and read-out circuits is used to control a subset of the qubits and to read out data from the subset of qubits.
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公开(公告)号：US11621340B2
公开(公告)日：2023-04-04
申请号：US16681141
申请日：2019-11-12
摘要： The present disclosure relates to a method for fabricating a field-effect transistor structure on a substrate. The method includes forming a first semiconductor structure on the substrate, forming above the first semiconductor structure a gate structure that comprises a spacer layer laterally terminating the gate structure and has a lower etch rate than the first semiconductor structure with respect to a predetermined etchant, forming an undercut below the spacer layer by recessing the first semiconductor structure using the etchant, the undercut extending laterally below the spacer layer by not more than the thickness of the spacer layer, forming on the first semiconductor structure a second semiconductor structure filling the undercut, and forming a third semiconductor structure above the first semiconductor structure, wherein one of the second and third semiconductor structures forms the source of the field-effect transistor structure and the other one forms the drain.
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公开(公告)号：US20220302269A1
公开(公告)日：2022-09-22
申请号：US17203971
申请日：2021-03-17
IPC分类号： H01L29/417 , H01L29/06 , H01L29/423 , H01L21/8238
摘要： A method for forming heterogeneous complementary FETs using a compact stacked nanosheet process is disclosed. The method comprises forming a first nanosheet stack comprising two layers of a first channel material separated by a second sacrificial layer, forming over the first nanosheet stack an equivalent second nanosheet stack, wherein the first channel material is complementary to the second channel material. The method comprises further forming a first source region and a first drain region, thereby building a first FET, and forming over the first source region and the first drain region a second source region and a second drain region, thereby building a second FET, removing selectively sacrificial layers, and forming a gate stack comprising a gate-all-around structure around all channels.
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公开(公告)号：US11201246B2
公开(公告)日：2021-12-14
申请号：US16681225
申请日：2019-11-12
发明人： Clarissa Convertino , Cezar Bogdan Zota , Kirsten Emilie Moselund , Lukas Czornomaz , Davide Cutaia
IPC分类号： H01L29/786 , H01L29/66 , H01L29/08 , H01L29/40 , H01L21/8234
摘要： The present disclosure relates to a method for fabricating an FET structure. The method includes forming on a substrate a first semiconductor structure and an insulator structure covering the first semiconductor structure with a first insulator layer, forming on the first insulator layer a sacrificial layer extending to a reference plane, forming a second insulator layer on the reference plane, forming a first cavity through the second insulator layer, the sacrificial layer and the first insulator layer, thus exposing a surface of the first semiconductor structure, filling the first cavity with a second semiconductor structure extending from the surface at least up to the first reference plane, forming a third semiconductor structure on the second semiconductor structure, selectively removing the sacrificial layer, thus forming a second cavity, and filling the second cavity with a gate structure.
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公开(公告)号：US20210175234A1
公开(公告)日：2021-06-10
申请号：US16703916
申请日：2019-12-05
IPC分类号： H01L27/108 , G11C11/404
摘要： The invention relates to a capacitorless DRAM cell, the cell comprising a heterostructure, a gate structure adjoining the heterostructure in a first direction, a drain structure adjoining the heterostructure in a second direction perpendicular to the first direction, and a source structure adjoining the heterostructure in the direction opposite the second direction, the heterostructure comprising one or more semiconducting channel layers and one or more electrically insulating barrier layers, the channel layers and the barrier layers being alternatingly stacked in the first direction.
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公开(公告)号：US20210143263A1
公开(公告)日：2021-05-13
申请号：US16681141
申请日：2019-11-12
摘要： The present disclosure relates to a method for fabricating a field-effect transistor structure on a substrate. The method includes forming a first semiconductor structure on the substrate, forming above the first semiconductor structure a gate structure that comprises a spacer layer laterally terminating the gate structure and has a lower etch rate than the first semiconductor structure with respect to a predetermined etchant, forming an undercut below the spacer layer by recessing the first semiconductor structure using the etchant, the undercut extending laterally below the spacer layer by not more than the thickness of the spacer layer, forming on the first semiconductor structure a second semiconductor structure filling the undercut, and forming a third semiconductor structure above the first semiconductor structure, wherein one of the second and third semiconductor structures forms the source of the field-effect transistor structure and the other one forms the drain.
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