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公开(公告)号：US20230139805A1
公开(公告)日：2023-05-04
申请号：US17453499
申请日：2021-11-04
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Thomas Morf , Cezar Bogdan Zota , Peter Mueller , Pier Andrea Francese , Marcel A. Kossel , Matthias Braendli , Mridula Prathapan
Abstract: The invention relates to a control unit for controlling a data transfer between a classical processor and a quantum processor with a plurality of qubits. The control unit comprises a plurality of control and read-out circuits configured for controlling and reading out the plurality of qubits. Each of the control and read-out circuits is assigned to one or more of the qubits. A controlling of the quantum processor by the control unit comprises selectively powering on a subset of the control and read-out circuits during an instruction cycle, while ensuring that the remaining control and read-out circuits are powered off during the instruction cycle. The powered-on subset of control and read-out circuits is used to control a subset of the qubits and to read out data from the subset of qubits.
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公开(公告)号：US12095473B2
公开(公告)日：2024-09-17
申请号：US18053940
申请日：2022-11-09
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Abdullah Serdar Yonar , Pier Andrea Francese , Marcel A. Kossel , Mridula Prathapan , Matthias Braendli , Thomas Morf
CPC classification number: H03M1/50 , H03M1/1009 , H03M1/1215 , H03M1/1245
Abstract: The invention is notably directed to a voltage-to-time converter comprising a first interleaving stage configured to perform a sampling of an input voltage, thereby generating a first set of sampled voltage signals. The first interleaving stage is further configured to perform a first voltage-to-time conversion in an interleaved manner, thereby generating a first set of time-interleaved signals in the time domain. A second interleaving stage is configured to perform a time-to-voltage conversion of the first set of time-interleaved signals, thereby generating a second set of sampled voltage signals. The second interleaving stage is further configured perform a second voltage-to-time conversion in an interleaved manner, thereby generating a second set of time-interleaved signals in the time domain.
The invention further concerns a related design structure and a related method.-
Patent Agency Ranking
公开(公告)号：US11816062B2
公开(公告)日：2023-11-14
申请号：US17453499
申请日：2021-11-04
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Thomas Morf , Cezar Bogdan Zota , Peter Mueller , Pier Andrea Francese , Marcel A. Kossel , Matthias Braendli , Mridula Prathapan
Abstract: The invention relates to a control unit for controlling a data transfer between a classical processor and a quantum processor with a plurality of qubits. The control unit comprises a plurality of control and read-out circuits configured for controlling and reading out the plurality of qubits. Each of the control and read-out circuits is assigned to one or more of the qubits. A controlling of the quantum processor by the control unit comprises selectively powering on a subset of the control and read-out circuits during an instruction cycle, while ensuring that the remaining control and read-out circuits are powered off during the instruction cycle. The powered-on subset of control and read-out circuits is used to control a subset of the qubits and to read out data from the subset of qubits.
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公开(公告)号：US20240154620A1
公开(公告)日：2024-05-09
申请号：US18053940
申请日：2022-11-09
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Abdullah Serdar Yonar , Pier Andrea Francese , Marcel A. Kossel , Mridula Prathapan , Matthias Braendli , Thomas Morf
IPC: H03M1/50
CPC classification number: H03M1/50
Abstract: The invention is notably directed to a voltage-to-time converter comprising a first interleaving stage configured to perform a sampling of an input voltage, thereby generating a first set of sampled voltage signals. The first interleaving stage is further configured to perform a first voltage-to-time conversion in an interleaved manner, thereby generating a first set of time-interleaved signals in the time domain. A second interleaving stage is configured to perform a time-to-voltage conversion of the first set of time-interleaved signals, thereby generating a second set of sampled voltage signals. The second interleaving stage is further configured perform a second voltage-to-time conversion in an interleaved manner, thereby generating a second set of time-interleaved signals in the time domain.
The invention further concerns a related design structure and a related method.-
公开(公告)号：US11057039B1
公开(公告)日：2021-07-06
申请号：US16949325
申请日：2020-10-26
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Marcel A. Kossel , Vishal Khatri , Pier Andrea Francese , Matthias Braendli
Abstract: The present disclosure relates to a method for quadrature error correction using a frequency divider circuit. The method comprises delaying input of data to master input terminals and/or slave input terminals of the frequency divider circuit for correcting a quadrature error between the in-phase and quadrature-phase output signals.
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公开(公告)号：US20160358635A1
公开(公告)日：2016-12-08
申请号：US14729100
申请日：2015-06-03
Applicant: International Business Machines Corporation
Inventor： Matthias Braendli , Marcel A. Kossel
IPC: G11C5/14 , G11C11/4074
CPC classification number: G11C5/147 , G11C7/14 , G11C11/4074 , G11C29/028
Abstract: The invention relates to a receiving unit for performing a calibration of a reference voltage, comprising a reference voltage unit for generating and applying a reference voltage on the evaluation unit depending on a converter value, an evaluation unit for receiving a single-ended data signal and being configured to determine an evaluation signal based on the data signal and the reference voltage, and a logic unit configured to perform a calibration process for calibrating the reference voltage. The logic unit is configured to command a memory device to apply a permanent digital logical state on a data line, to iteratively adapt a converter voltage to substantially match the voltage level of the logical state on the data line, and to determine the reference voltage depending on the converter voltage for which the voltage level of the logical state on the data line has been substantially matched.
Abstract translation: 本发明涉及一种用于执行参考电压校准的接收单元，包括用于根据转换器值在评估单元上产生和施加参考电压的参考电压单元，用于接收单端数据信号的评估单元和 被配置为基于所述数据信号和所述参考电压来确定评估信号，以及逻辑单元，被配置为执行用于校准所述参考电压的校准处理。 逻辑单元被配置为命令存储器件在数据线上施加永久数字逻辑状态，以迭代地适配转换器电压以使数据线上的逻辑状态的电压电平基本匹配，并且确定参考电压依赖 在数据线上的逻辑状态的电压电平基本匹配的转换器电压上。
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公开(公告)号：US09496008B1
公开(公告)日：2016-11-15
申请号：US14729100
申请日：2015-06-03
Applicant: International Business Machines Corporation
Inventor： Matthias Braendli , Marcel A. Kossel
IPC: G11C5/14 , G11C11/4074
CPC classification number: G11C5/147 , G11C7/14 , G11C11/4074 , G11C29/028
Abstract: The invention relates to a receiving unit for performing a calibration of a reference voltage, comprising a reference voltage unit for generating and applying a reference voltage on the evaluation unit depending on a converter value, an evaluation unit for receiving a single-ended data signal and being configured to determine an evaluation signal based on the data signal and the reference voltage, and a logic unit configured to perform a calibration process for calibrating the reference voltage. The logic unit is configured to command a memory device to apply a permanent digital logical state on a data line, to iteratively adapt a converter voltage to substantially match the voltage level of the logical state on the data line, and to determine the reference voltage depending on the converter voltage for which the voltage level of the logical state on the data line has been substantially matched.
Abstract translation: 本发明涉及一种用于执行参考电压校准的接收单元，包括用于根据转换器值在评估单元上产生和施加参考电压的参考电压单元，用于接收单端数据信号的评估单元和 被配置为基于所述数据信号和所述参考电压来确定评估信号，以及逻辑单元，被配置为执行用于校准所述参考电压的校准处理。 逻辑单元被配置为命令存储器件在数据线上施加永久数字逻辑状态，以迭代地适配转换器电压以使数据线上的逻辑状态的电压电平基本匹配，并且确定参考电压依赖 在数据线上的逻辑状态的电压电平基本匹配的转换器电压上。
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