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公开(公告)号:US12182274B2
公开(公告)日:2024-12-31
申请号:US18382107
申请日:2023-10-20
Applicant: International Business Machines Corporation
Inventor: Pin-Yu Chen , Sijia Liu , Lingfei Wu , Chia-Yu Chen
IPC: G06F21/57 , G06N3/04 , G06N3/08 , G06V10/764 , G06V10/82
Abstract: An adversarial robustness testing method, system, and computer program product include testing, via an accelerator, a robustness of a black-box system under different access settings, where the testing includes tearing down the robustness testing to a subtask of a predetermined size.
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公开(公告)号:US20240045974A1
公开(公告)日:2024-02-08
申请号:US18382107
申请日:2023-10-20
Applicant: International Business Machines Corporation
Inventor: Pin-Yu Chen , Sijia Liu , Lingfei Wu , Chia-Yu Chen
IPC: G06F21/57 , G06N3/04 , G06N3/08 , G06V10/764 , G06V10/82
CPC classification number: G06F21/577 , G06N3/04 , G06N3/08 , G06V10/764 , G06V10/82 , G06F2221/034
Abstract: An adversarial robustness testing method, system, and computer program product include testing, via an accelerator, a robustness of a black-box system under different access settings, where the testing includes tearing down the robustness testing to a subtask of a predetermined size.
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公开(公告)号:US20220180171A1
公开(公告)日:2022-06-09
申请号:US17112528
申请日:2020-12-04
Applicant: International Business Machines Corporation
Inventor: Xiao Sun , Ankur Agrawal , Kailash Gopalakrishnan , Naigang Wang , Chia-Yu Chen , Jiamin Ni
Abstract: An apparatus includes a floating-point gradient register; an integer register; a memory bank; and an array of processing units. Each of the units includes a plurality of binary shifters having an integer input configured to obtain corresponding bits of a 4-bit integer multiplicand, and a shift-specifying input configured to obtain corresponding bits in an exponent field of a 4-bit floating point multiplier. The multiplier is specified in a mantissaless four-bit floating point format including a sign bit, three exponent bits, and no mantissa bits. An adder tree has a plurality of inputs coupled to outputs of the plurality of shifters, and a rounder has an input coupled to an output of the adder tree. The integer inputs are connected to the integer register; the shift-specifying inputs are connected to the floating-point gradient register; and outputs of the rounders are coupled to the memory bank.
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公开(公告)号:US11295208B2
公开(公告)日:2022-04-05
申请号:US15830170
申请日:2017-12-04
Applicant: International Business Machines Corporation
Inventor: Ankur Agrawal , Daniel Brand , Chia-Yu Chen , Jungwook Choi , Kailash Gopalakrishnan
Abstract: Embodiments of the present invention provide a computer-implemented method for adaptive residual gradient compression for training of a deep learning neural network (DNN). The method includes obtaining, by a first learner, a current gradient vector for a neural network layer of the DNN, in which the current gradient vector includes gradient weights of parameters of the neural network layer that are calculated from a mini-batch of training data. A current residue vector is generated that includes residual gradient weights for the mini-batch. A compressed current residue vector is generated based on dividing the residual gradient weights of the current residue vector into a plurality of bins of a uniform size and quantizing a subset of the residual gradient weights of one or more bins of the plurality of bins. The compressed current residue vector is then transmitted to a second learner of the plurality of learners or to a parameter server.
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公开(公告)号:US20210117771A1
公开(公告)日:2021-04-22
申请号:US16657263
申请日:2019-10-18
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor: Chia-Yu Chen , Pin-Yu Chen , Mingu Kang , Jintao Zhang
Abstract: Methods, systems, and circuits for training a neural network include applying noise to a set of training data across wordlines using a respective noise switch on each wordline. A neural network is trained using the noise-applied training data to generate a classifier that is robust against adversarial training.
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公开(公告)号:US20210064976A1
公开(公告)日:2021-03-04
申请号:US16558554
申请日:2019-09-03
Applicant: International Business Machines Corporation
Inventor: Xiao Sun , Jungwook Choi , Naigang Wang , Chia-Yu Chen , Kailash Gopalakrishnan
Abstract: An apparatus includes circuitry for a neural network that is configured to perform forward propagation neural network operations on floating point numbers having a first n-bit floating point format. The first n-bit floating point format has a configuration consisting of a sign bit, m exponent bits and p mantissa bits where m is greater than p. The circuitry is further configured to perform backward propagation neural network operations on floating point numbers having a second n-bit floating point format that is different than the first n-bit floating point format. The second n-bit floating point format has a configuration consisting of a sign bit, q exponent bits and r mantissa bits where q is greater than m and r is less than p.
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公开(公告)号:US10529717B2
公开(公告)日:2020-01-07
申请号:US14865667
申请日:2015-09-25
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor: Chia-Yu Chen , Bruce B. Doris , Hong He , Rajasekhar Venigalla
IPC: H01L29/04 , H01L29/66 , H01L29/78 , H01L27/092 , H01L21/18 , H01L29/165 , H01L21/8238 , H01L21/84 , H01L27/12
Abstract: A semiconductor device that includes at least one germanium containing fin structure having a length along a direction and a sidewall orientated along the (100) plane. The semiconductor device also includes at least one germanium free fin structure having a length along a direction and a sidewall orientated along the (100) plane. A gate structure is present on a channel region of each of the germanium containing fin structure and the germanium free fin structure. N-type epitaxial semiconductor material having a square geometry present on the source and drain portions of the sidewalls having the (100) plane orientation of the germanium free fin structures. P-type epitaxial semiconductor material having a square geometry is present on the source and drain portions of the sidewalls having the (100) plane orientation of the germanium containing fin structures.
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公开(公告)号:US20190171935A1
公开(公告)日:2019-06-06
申请号:US15830170
申请日:2017-12-04
Applicant: International Business Machines Corporation
Inventor: Ankur Agrawal , Daniel Brand , Chia-Yu Chen , Jungwook Choi , Kailash Gopalakrishnan
Abstract: Embodiments of the present invention provide a computer-implemented method for adaptive residual gradient compression for training of a deep learning neural network (DNN). The method includes obtaining, by a first learner, a current gradient vector for a neural network layer of the DNN, in which the current gradient vector includes gradient weights of parameters of the neural network layer that are calculated from a mini-batch of training data. A current residue vector is generated that includes residual gradient weights for the mini-batch. A compressed current residue vector is generated based on dividing the residual gradient weights of the current residue vector into a plurality of bins of a uniform size and quantizing a subset of the residual gradient weights of one or more bins of the plurality of bins. The compressed current residue vector is then transmitted to a second learner of the plurality of learners or to a parameter server.
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公开(公告)号:US10229982B2
公开(公告)日:2019-03-12
申请号:US15629910
申请日:2017-06-22
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor: Chia-Yu Chen , Zuoguang Liu , Sanjay C. Mehta , Tenko Yamashita
IPC: H01L29/45 , H01L29/08 , H01L29/16 , H01L29/40 , H01L29/41 , H01L29/49 , H01L29/51 , H01L29/66 , H01L29/78 , H01L23/48 , H01L21/768 , H01L21/225 , H01L29/417 , H01L21/8238 , H01L21/3065 , H01L21/311 , H01L29/167 , H01L21/285 , H01L23/485
Abstract: A semiconductor device includes a gate disposed over a substrate; a source region and a drain region on opposing sides of the gate; and a pair of trench contacts over and abutting an interfacial layer portion of at least one of the source region and the drain region; wherein the interfacial layer includes boron in an amount in a range from about 5×1021 to about 5×1022 atoms/cm2.
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公开(公告)号:US10177167B2
公开(公告)日:2019-01-08
申请号:US15202940
申请日:2016-07-06
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor: Chia-Yu Chen , Bruce B. Doris , Hong He , Rajasekhar Venigalla
IPC: H01L29/66 , H01L27/12 , H01L29/78 , H01L27/092 , H01L21/8238 , H01L21/84 , H01L21/02 , H01L29/04 , H01L29/165 , H01L29/06 , H01L29/08 , H01L29/161 , H01L21/308
Abstract: A method for forming a hybrid complementary metal oxide semiconductor (CMOS) device includes orienting a semiconductor layer of a semiconductor-on-insulator (SOI) substrate with a base substrate of the SOI, exposing the base substrate in an N-well region by etching through a mask layer, a dielectric layer, the semiconductor layer and a buried dielectric to form a trench and forming spacers on sidewalls of the trench. The base substrate is epitaxially grown from a bottom of the trench to form an extended region. A fin material is epitaxially grown from the extended region within the trench. The mask layer and the dielectric layer are restored over the trench. P-type field-effect transistor (PFET) fins are etched on the base substrate, and N-type field-effect transistor (NFET) fins are etched in the semiconductor layer.
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