公开(公告)号：US20230178624A1

公开(公告)日：2023-06-08

申请号：US17643014

申请日：2021-12-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： GEN TSUTSUI ,  SHOGO MOCHIZUKI

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L29/42392 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/78696

Abstract: Embodiments are disclosed for a system. The system includes a semiconductor structure. The semiconductor structure includes a stacked field effect transistor (stacked-FET). The stacked-FET includes a top FET having multiple top channels having multiple nano-sheets in contact with corresponding nano-sheets in a corresponding top channels for an active gate. The stacked-FET includes multiple bottom channels having a dielectric material. The semiconductor structure also includes an active gate. The active gate includes the corresponding top channels and corresponding bottom channels having the dielectric material.

公开(公告)号：US20190019796A1

公开(公告)日：2019-01-17

申请号：US16117811

申请日：2018-08-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： ZUOGUANG LIU ,  GEN TSUTSUI ,  HENG WU ,  PENG XU

IPC: H01L27/11 ,  H01L27/092 ,  H01L21/324 ,  H01L21/265 ,  H01L29/08 ,  H01L29/167 ,  H01L21/02 ,  H01L21/8238

Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures having a shared SRAM trench and a common contact having a low contact resistance. The method includes forming a first semiconductor fin opposite a surface of a substrate and forming a second semiconductor fin opposite the surface of the substrate and adjacent to the first semiconductor fin. A doped region is formed over portions of each of the first and second semiconductor fins and a dielectric layer is formed over the doped regions. A shared trench is formed in the dielectric layer exposing portions of the doped regions. The exposed doped regions are then amorphized and recrystallized.

公开(公告)号：US20170133272A1

公开(公告)日：2017-05-11

申请号：US14968134

申请日：2015-12-14

Applicant: International Business Machines Corporation

Inventor： RUQIANG BAO ,  GAURI KARVE ,  DERRICK LIU ,  ROBERT R. ROBISON ,  GEN TSUTSUI ,  REINALDO A. VEGA ,  KOJI WATANABE

IPC: H01L21/8234 ,  H01L21/02 ,  H01L29/40

CPC classification number: H01L27/0922 ,  H01L21/02192 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/16 ,  H01L29/161 ,  H01L29/401 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7856

Abstract: A method of making a semiconductor device comprises forming a first channel region comprising a first channel region material and a second channel region comprising a second channel region material; disposing a gate dielectric on the first channel region and second channel region; depositing a work function modifying material on the gate dielectric; disposing a mask over the work function modifying material deposited on the gate dielectric disposed on the first channel region; removing the work function modifying material from the unmasked gate dielectric disposed on the second channel region; removing the mask from the work function modifying material deposited on the gate dielectric disposed on the first channel region; forming a first gate electrode on the work function modifying material deposited on the first channel region and forming a second gate electrode on the gate dielectric disposed on the second channel region.

公开(公告)号：US20230307447A1

公开(公告)日：2023-09-28

申请号：US17655807

申请日：2022-03-22

Applicant: International Business Machines Corporation

Inventor： GEN TSUTSUI ,  Albert M. Young ,  Su Chen Fan ,  Junli Wang ,  Brent A. Anderson

IPC: H01L27/06 ,  H01L27/092 ,  H01L29/417 ,  H01L29/40

CPC classification number: H01L27/0688 ,  H01L27/092 ,  H01L29/401 ,  H01L29/41725

Abstract: An approach forming semiconductor structure composed of one or more stacked semiconductor devices that include at least a top semiconductor device, a bottom semiconductor device under the top semiconductor, and contacts to each of the semiconductor devices. The approach provides a stacked semiconductor structure where the bottom semiconductor device is wider than the top semiconductor device. The approach also provides the stacked semiconductor structure where the width of the top semiconductor device is the same as the width of the bottom semiconductor device. The approach includes forming a contact to a side of the bottom semiconductor device when the width of the top semiconductor device is the same as the bottom semiconductor device. The approach includes forming a contact to epitaxy grown on a portion of the top and a side of the bottom semiconductor device when the bottom semiconductor device is larger than the top semiconductor device.

公开(公告)号：US20170133372A1

公开(公告)日：2017-05-11

申请号：US14934758

申请日：2015-11-06

Applicant: International Business Machines Corporation

Inventor： RUQIANG BAO ,  GAURI KARVE ,  DERRICK LIU ,  ROBERT R. ROBISON ,  GEN TSUTSUI ,  REINALDO A. VEGA ,  KOJI WATANABE

IPC: H01L27/092 ,  H01L29/161 ,  H01L29/16 ,  H01L29/49

CPC classification number: H01L27/0922 ,  H01L21/02192 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/16 ,  H01L29/161 ,  H01L29/401 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7856

Abstract: A method of making a semiconductor device comprises forming a first channel region comprising a first channel region material and a second channel region comprising a second channel region material; disposing a gate dielectric on the first channel region and second channel region; depositing a work function modifying material on the gate dielectric; disposing a mask over the work function modifying material deposited on the gate dielectric disposed on the first channel region; removing the work function modifying material from the unmasked gate dielectric disposed on the second channel region; removing the mask from the work function modifying material deposited on the gate dielectric disposed on the first channel region; forming a first gate electrode on the work function modifying material deposited on the first channel region and forming a second gate electrode on the gate dielectric disposed on the second channel region.