公开(公告)号：US20240128345A1

公开(公告)日：2024-04-18

申请号：US17964115

申请日：2022-10-12

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Ruilong Xie ,  Su Chen Fan ,  Ravikumar Ramachandran ,  Julien Frougier

IPC分类号： H01L29/423 ,  H01L21/768 ,  H01L21/8238 ,  H01L29/786

CPC分类号： H01L29/42392 ,  H01L21/76834 ,  H01L21/76885 ,  H01L21/823871 ,  H01L29/78696

摘要： A semiconductor structure is presented including a plurality of field effect transistor (FET) devices, each FET device having a different gate threshold voltage, first spacers disposed on sidewalls of each FET device, second spacers disposed over and in direct contact with the first spacers, the second spacers having a width greater than a width of the first spacers, and a gate contact directly contacting an FET device of the plurality of FET devices, where only an upper portion of the gate contact directly contacts third spacers on opposed ends thereof. The second spacers can have a bi-layer configuration and the gate contact wraps around a top portion of the FET device in direct contact with the gate contact.

公开(公告)号：US20240113176A1

公开(公告)日：2024-04-04

申请号：US17937967

申请日：2022-10-04

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Ruilong Xie ,  Lawrence A. Clevenger ,  Brent A. Anderson ,  Kisik Choi ,  Su Chen Fan ,  Shogo Mochizuki ,  SON NGUYEN

IPC分类号： H01L29/417 ,  H01L23/528 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L29/775

CPC分类号： H01L29/41733 ,  H01L23/5286 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/66439 ,  H01L29/775

摘要： A semiconductor device includes a field effect transistor (FET). The FET includes a gate and a first source or drain (S/D) region. A frontside S/D contact may be connected to and extend vertically upward from a top surface of the first S/D region. The FET further includes a second S/D region. The second S/D region includes a conduit liner and an inner column internal to the conduit liner that extends below a bottom surface of the wraparound gate. A backside S/D contact may be connected to and extend vertically downward from a bottom surface of the second S/D region.

公开(公告)号：US20240112985A1

公开(公告)日：2024-04-04

申请号：US17937955

申请日：2022-10-04

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Ruilong Xie ,  Lawrence A. Clevenger ,  Brent A. Anderson ,  Kisik Choi ,  Su Chen Fan ,  Shogo Mochizuki ,  SON NGUYEN

IPC分类号： H01L23/48 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L23/481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

摘要： A semiconductor device includes a nanostructure field effect transistor (FET). The FET includes a gate and a first source or drain (S/D) region. A frontside S/D contact may be connected to and extends vertically upward from a top surface of the first S/D region. The FET further includes a second S/D region. The second S/D region extends below a bottom surface of the gate. A backside S/D contact may be connected to and extend vertically downward from a bottom surface of the second S/D region.

公开(公告)号：US20240079461A1

公开(公告)日：2024-03-07

申请号：US17823969

申请日：2022-09-01

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Brent A. Anderson ,  Su Chen Fan ,  Jay William Strane ,  Ruilong Xie

IPC分类号： H01L29/417 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/41741 ,  H01L29/401 ,  H01L29/66515 ,  H01L29/66666 ,  H01L29/7827

摘要： A semiconductor structure including a fin of a vertical transistor structure, a top source drain region on a top side of the fin, a bottom source drain region on a bottom side of the fin, and a backside contact below and contacting the bottom source drain region.

公开(公告)号：US20240014135A1

公开(公告)日：2024-01-11

申请号：US17860082

申请日：2022-07-07

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Junli Wang ,  Albert M. Chu ,  Albert M. Young ,  Chen Zhang ,  Su Chen Fan ,  Ruilong Xie

IPC分类号： H01L23/528 ,  H01L23/48 ,  H01L21/8234 ,  H01L29/786

CPC分类号： H01L23/5286 ,  H01L23/481 ,  H01L21/823475 ,  H01L29/78696

摘要： A semiconductor device including a first source/drain region (S/D) located on a frontside of a substrate, wherein the first source/drain region has a first width, a second S/D region located on the frontside of the substrate, wherein the second source/drain region is located above the first source drain region, wherein the second source/drain region has second width, wherein the first width is larger than the second width, a first power rail located on a backside of the substrate, a second power rail located on the backside of the substrate, a first connector in contact with the first source/drain region, wherein the first connector is only in contact with a sidewall of the first source/drain region, and a second connector in contact with the second source/drain region, wherein the second connector is in contact with a top surface and a side surface of the second source/drain region.

公开(公告)号：US20230411477A1

公开(公告)日：2023-12-21

申请号：US17807873

申请日：2022-06-21

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Su Chen Fan ,  Nicolas Jean Loubet ,  Yann Mignot ,  Tsung-Sheng Kang ,  Eric Miller

IPC分类号： H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/45 ,  H01L29/417

CPC分类号： H01L29/42392 ,  H01L29/0665 ,  H01L29/41775 ,  H01L29/458 ,  H01L29/78696

摘要： A gate-all-around transistor structure including a channel region surrounded on three sides by a gate conductor, and a pair of salicide regions extending from opposite ends of the channel region in a direction parallel with the gate conductor.

公开(公告)号：US11694958B2

公开(公告)日：2023-07-04

申请号：US16891600

申请日：2020-06-03

申请人： International Business Machines Corporation

发明人： Huimei Zhou ,  Su Chen Fan ,  Miaomiao Wang ,  Zuoguang Liu

IPC分类号： H01L23/532 ,  H01L21/768

CPC分类号： H01L23/53266 ,  H01L21/76846 ,  H01L21/76849 ,  H01L23/53238

摘要： Semiconductor device layout designs for Vt tuning are provided. In one aspect, a semiconductor device is provided. The semiconductor device includes: at least one first metal line in contact with a source or drain of an FET; at least one second metal line in contact with a gate of the FET, wherein the first metal line crosses the second metal line; and an oxygen diffusion blocking layer on top of the at least one first metal line in an overlap area of the at least one first metal line and the at least one second metal line. A method of forming a semiconductor device is also provided.

公开(公告)号：US20230100368A1

公开(公告)日：2023-03-30

申请号：US17483922

申请日：2021-09-24

申请人： International Business Machines Corporation

发明人： Hsueh-Chung Chen ,  Yann Mignot ,  Su Chen Fan ,  Mary Claire Silvestre ,  Chi-Chun LIU ,  Junli Wang

IPC分类号： H01L23/522 ,  H01L21/768

摘要： A device includes: a first dielectric material; a first metal line in the first dielectric material; a second dielectric material disposed on the first dielectric material and the first metal line; a second metal line in the second dielectric material; and a plurality of metal vias disposed on a same level and connecting the first metal line and the second metal line, wherein the plurality of metal vias comprise a first top via and a bottom via having different sidewall profile angles.

公开(公告)号：US20220406776A1

公开(公告)日：2022-12-22

申请号：US17304392

申请日：2021-06-21

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Ruilong Xie ,  Eric Miller ,  Dechao Guo ,  Jeffrey C. Shearer ,  Su Chen Fan ,  Julien Frougier ,  Veeraraghavan S. Basker ,  Junli Wang ,  Sung Dae Suk

IPC分类号： H01L27/092 ,  H01L29/04 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

摘要： A semiconductor device comprising at least one first gate all around channel having a horizontal physical orientation, wherein the at least one first gate all around channel is comprised of a first material, wherein the at least one first gate all around channel has a sidewall surface with (100) crystal orientation. At least one second gate all around channel having a vertical physical orientation, wherein the second channel is located above the at least one first gate all around channel, wherein the at least one second gate all around channel is comprised of a second material, wherein the at least one second gate all around channel has a sidewall surface with (110) crystal orientation. A gate metal enclosing the at least one first gate all around channel and the at least one second gate all around channel.

公开(公告)号：US20220181321A1

公开(公告)日：2022-06-09

申请号：US17113674

申请日：2020-12-07

申请人： International Business Machines Corporation

发明人： Tsung-Sheng Kang ,  Ardasheir Rahman ,  Tao Li ,  Su Chen Fan

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H03K19/173 ,  H03K19/20 ,  H01L29/78 ,  H01L29/66

摘要： A semiconductor structure comprises two or more vertical fins, a bottom epitaxial layer surrounding a bottom portion of a given one of the two or more vertical fins, a top epitaxial layer surrounding a top portion of the given one of the two or more vertical fins, a shared epitaxial layer surrounding a middle portion of the given one of the two or more vertical fins, and a connecting layer contacting the bottom epitaxial layer and the top epitaxial layer, the connecting layer being disposed to a lateral side of the two or more vertical fins.