公开(公告)号：US20190019796A1

公开(公告)日：2019-01-17

申请号：US16117811

申请日：2018-08-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： ZUOGUANG LIU ,  GEN TSUTSUI ,  HENG WU ,  PENG XU

IPC: H01L27/11 ,  H01L27/092 ,  H01L21/324 ,  H01L21/265 ,  H01L29/08 ,  H01L29/167 ,  H01L21/02 ,  H01L21/8238

Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures having a shared SRAM trench and a common contact having a low contact resistance. The method includes forming a first semiconductor fin opposite a surface of a substrate and forming a second semiconductor fin opposite the surface of the substrate and adjacent to the first semiconductor fin. A doped region is formed over portions of each of the first and second semiconductor fins and a dielectric layer is formed over the doped regions. A shared trench is formed in the dielectric layer exposing portions of the doped regions. The exposed doped regions are then amorphized and recrystallized.

公开(公告)号：US20200051850A1

公开(公告)日：2020-02-13

申请号：US16598458

申请日：2019-10-10

Applicant: International Business Machines Corporation

Inventor： KANGGUO CHENG ,  EKMINI A. DE SILVA ,  JUNTAO LI ,  YI SONG ,  PENG XU

IPC: H01L21/768 ,  H01L21/311 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/762

Abstract: A method and structure of forming air gaps with a sidewall image transfer process such as self-aligned double patterning to reduce capacitances. Different materials can be provided in the mandrel and non-mandrel regions to enlarge a process window for metal line end formation.

公开(公告)号：US20190371654A1

公开(公告)日：2019-12-05

申请号：US15992339

申请日：2018-05-30

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  PENG XU ,  EKMINI A. DE SILVA ,  Ruilong Xie

IPC: H01L21/768 ,  H01L23/522 ,  H01L29/417

Abstract: A semiconductor device is formed where a conductive extension (e.g., a TS) electrically couples with a first structure (e.g., an S/D) of the semiconductor device, a dielectric is deposited at least on a surface of a second structure (e.g., a gate), where the surface is substantially parallel to a plane of fabrication of the semiconductor device. An insulator cap surrounds an exposed portion of the extension. An opening is formed in the insulator cap, and a first contact (e.g., a CA) is formed through the opening to electrically couple with the first structure. A second contact (e.g., a CB) is formed through an opening in the dielectric at a first portion of the surface and electrically couples with the second structure. The dielectric continues to cover a second portion of the surface, and a portion of the insulator cap is interposed between the first contact and the second contact.

公开(公告)号：US20190214459A1

公开(公告)日：2019-07-11

申请号：US15868003

申请日：2018-01-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： KANGGUO CHENG ,  CHOONGHYUN LEE ,  JUNTAO LI ,  PENG XU

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/423

Abstract: A sacrificial gate stack for forming a nanosheet transistor includes a substrate. first, second and third silicon channel nanosheets formed over the substrate, and a first sandwich of germanium (Ge) containing layers disposed between the substrate and first silicon channel nanosheet. The stack also includes a second sandwich of Ge containing layers disposed between the first silicon channel nanosheet and the second silicon channel nanosheet; and a third sandwich of Ge containing layers disposed between the second silicon channel nanosheet and the third silicon channel nanosheet. Each sandwich includes first and second low Ge containing layers surrounding a silicon germanium (SiGe) sacrificial nanosheet that has a higher Ge concentration than the first and second low Ge containing layers.

公开(公告)号：US20200098860A1

公开(公告)日：2020-03-26

申请号：US16680633

申请日：2019-11-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： KANGGUO CHENG ,  CHOONGHYUN LEE ,  JUNTAO LI ,  PENG XU

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786 ,  B82Y10/00 ,  H01L29/423 ,  H01L29/78 ,  H01L21/02

Abstract: A sacrificial gate stack for forming a nanosheet transistor includes a substrate. first, second and third silicon channel nanosheets formed over the substrate, and a first sandwich of germanium (Ge) containing layers disposed between the substrate and first silicon channel nanosheet. The stack also includes a second sandwich of Ge containing layers disposed between the first silicon channel nanosheet and the second silicon channel nanosheet; and a third sandwich of Ge containing layers disposed between the second silicon channel nanosheet and the third silicon channel nanosheet. Each sandwich includes first and second low Ge containing layers surrounding a silicon germanium (SiGe) sacrificial nanosheet that has a higher Ge concentration than the first and second low Ge containing layers.

公开(公告)号：US20200066882A1

公开(公告)日：2020-02-27

申请号：US16666590

申请日：2019-10-29

Applicant: International Business Machines Corporation

Inventor： ZHENXING BI ,  Kangguo Cheng ,  JUNTAO LI ,  PENG XU

IPC: H01L29/66 ,  H01L23/522 ,  H01L21/768 ,  H01L27/112 ,  H01L27/11582 ,  H01L21/311 ,  H01L29/417 ,  H01L29/78 ,  H01L29/08

Abstract: A method of forming a semiconductor device and resulting structures having closely packed vertical transistors with reduced contact resistance by forming a semiconductor structure on a doped region of a substrate, the semiconductor structure including a gate formed over a channel region of a semiconductor fin. A liner is formed on the gate and the semiconductor fin, and a dielectric layer is formed on the liner. Portions of the liner are removed to expose a top surface and sidewalls of the semiconductor fin and a sidewall of the dielectric layer. A recessed opening is formed by recessing portions of the liner from the exposed sidewall of the dielectric layer. A top epitaxy region is formed on the exposed portions of the semiconductor fin and dielectric layer such that an extension of the top epitaxy region fills the recessed opening. The top epitaxy region is confined between portions of the liner.