公开(公告)号：US20250040199A1

公开(公告)日：2025-01-30

申请号：US18359922

申请日：2023-07-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Brent A. Anderson ,  Albert M. Chu ,  Junli Wang ,  Jay William Strane

IPC: H01L29/06 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a first transistor having a first source/drain (S/D) region; a second transistor having a second S/D region, the second transistor being stacked on top of the first transistor; and a first S/D contact shared by the first S/D region of the first transistor and the second S/D region of the second transistor, where the first S/D contact has a first portion and a second portion, the first portion being in direct contact with a top surface of the first S/D region of the first transistor and in direct contact with a bottom surface of the second S/D region, and the second portion being in direct contact with an inner sidewall of the second S/D region of the second transistor. A method of manufacturing the semiconductor structure is also provided.

公开(公告)号：US20250006786A1

公开(公告)日：2025-01-02

申请号：US18214642

申请日：2023-06-27

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Brent A. Anderson ,  Junli Wang ,  Jay William Strane ,  Albert M. Chu

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device comprises a top field effect transistor (FET) and a bottom FET in a stacked profile. The semiconductor device also comprises a gate. The gate comprises two top-FET gate extensions and two bottom-FET gate extensions. The semiconductor device also comprises an insulator liner. The insulator liner interfaces with the two top-FET gate extensions and two bottom-FET gate extensions. The semiconductor device also comprises a dielectric that interfaces with the insulator liner.

公开(公告)号：US20250006736A1

公开(公告)日：2025-01-02

申请号：US18214682

申请日：2023-06-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Biswanath Senapati ,  Shahrukh Khan ,  Utkarsh Bajpai ,  Terence Hook ,  Chen Zhang ,  Junli Wang

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: A semiconductor cell comprises a top FET that contains a first set of silicon nanosheets and a bottom FET that contains a second set of silicon nanosheets. The top FET and bottom FET are in a stacked profile. The semiconductor cell comprises a top FET cutout region lateral to the first set of nanosheets and above a portion of the second set of nanosheets. The semiconductor cell also comprises a dielectric fill within the top FET cutout region.

公开(公告)号：US20240395816A1

公开(公告)日：2024-11-28

申请号：US18321838

申请日：2023-05-23

Applicant: International Business Machines Corporation

Inventor： Brent A. Anderson ,  Nicolas Jean Loubet ,  Shogo Mochizuki ,  Junli Wang

IPC: H01L27/092 ,  H01L21/8238 ,  H01L23/48 ,  H01L29/04 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

Abstract: Aspects of the invention are directed to fabrication methods and resulting structures for providing transistors having hybrid crystal orientation channels and mixed crystal orientation bottom epitaxies. In a non-limiting embodiment, a first fin having a first crystal orientation is formed in a first region of a substrate having a second crystal orientation. A second fin having the second crystal orientation is formed in a second region of the substrate. The second fin is formed directly on a surface of the substrate. A mixed crystal bottom source or drain region is formed between the first fin and the first region of the substrate and a single crystal bottom source or drain region having the second crystal orientation is formed on sidewalls of the second fin and on the surface of the substrate in the second region.

公开(公告)号：US12142656B2

公开(公告)日：2024-11-12

申请号：US17541894

申请日：2021-12-03

Applicant: International Business Machines Corporation

Inventor： Albert Chu ,  Junli Wang ,  Albert M. Young ,  Vidhi Zalani ,  Dechao Guo

IPC: H01L29/423 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/786

Abstract: A semiconductor structure includes a first transistor device comprising a plurality of channel regions. The semiconductor structure further includes a second transistor device comprising a plurality of channel regions. The first transistor device and the second transistor device are disposed in a stacked configuration. The plurality of channel regions of the first transistor device are disposed in a staggered configuration relative to the plurality of channel regions of the second transistor device.

公开(公告)号：US20240194601A1

公开(公告)日：2024-06-13

申请号：US18062624

申请日：2022-12-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Albert M. Chu ,  Nicholas Anthony Lanzillo ,  Albert M. Young ,  Junli Wang ,  Brent A. Anderson ,  Ruilong Xie ,  Lawrence A. Clevenger ,  REINALDO VEGA

IPC: H01L23/528 ,  G06F30/392 ,  G06F30/394 ,  H01L23/522 ,  H01L27/092

CPC classification number: H01L23/5286 ,  G06F30/392 ,  G06F30/394 ,  H01L23/5226 ,  H01L27/0922

Abstract: A semiconductor structure is presented having a plurality of circuit rows, a plurality of first power rails positioned on front sides of the plurality of circuit rows, a plurality of second power rails positioned on back sides of the plurality of circuit rows, and power tap cells associated with each the plurality of circuit rows, wherein each of the power tap cells includes one or more power vias connecting at least one first power rail of the plurality of first power rails to at least one second power rail of the plurality the second power rails. In one instance, the plurality of second power rails are orthogonal to the plurality of first power rails. in another instance, the plurality of first power rails are horizontally offset from the plurality of second power rails. The one or more power vias include at least two or more different sized power vias.

公开(公告)号：US12001772B2

公开(公告)日：2024-06-04

申请号：US17485088

申请日：2021-09-24

Applicant: International Business Machines Corporation

Inventor： Albert Chu ,  Junli Wang ,  Brent Anderson

IPC: G06F30/30 ,  G06F30/392 ,  H01L27/02 ,  G06F111/20

CPC classification number: G06F30/392 ,  H01L27/0207 ,  G06F2111/20

Abstract: Semiconductor integrated circuit devices are provided which have standard cells with ultra-short standard cell heights. For example, a device comprises an integrated circuit comprising a standard cell which comprises a first cell boundary and a second cell boundary. The standard cell comprises an n-track cell height defined by a distance between the first cell boundary and the second cell boundary, wherein n is four or less.

公开(公告)号：US20240164089A1

公开(公告)日：2024-05-16

申请号：US18054161

申请日：2022-11-10

Applicant: International Business Machines Corporation

Inventor： Albert M. Chu ,  Junli Wang ,  Albert M. Young ,  Brent A. Anderson ,  Ruilong Xie ,  Carl Radens

IPC: H01L27/112

CPC classification number: H01L27/11206

Abstract: Embodiments of the present invention are directed to processing methods and resulting structures having backside programmable memory cells. In a non-limiting embodiment, a front end of line structure having a plurality of programmable cells is formed such that each programmable cell includes a backside via in direct contact with a device region of the respective cell. A first portion of the backside vias defines one or more placeholder backside vias and a second portion defines one or more programmed backside vias. A back end of line structure (word line) is formed on a first surface of the front end of line structure. A backside structure is formed on a second surface of the front end of line structure opposite the first surface. The backside structure includes a backside metallization layer (bit line) in direct contact with the one or more programmed backside vias.

公开(公告)号：US20240162231A1

公开(公告)日：2024-05-16

申请号：US18054160

申请日：2022-11-10

Applicant: International Business Machines Corporation

Inventor： Albert M. Chu ,  Brent A. Anderson ,  Junli Wang ,  Albert M. Young ,  Ruilong Xie ,  Carl Radens

IPC: H01L27/118

CPC classification number: H01L27/11807 ,  H01L2027/11875 ,  H01L2027/11881

Abstract: Embodiments of the present invention are directed to processing methods and resulting structures for integrated circuits having backside programmable gate arrays. In a non-limiting embodiment, a front end of line structure having an array of transistors is formed such that each transistor of the array of transistors includes one or more placeholder backside vias. A first portion of the backside vias defines one or more placeholder backside vias and a second portion of the one or more backside vias defines one or more programmed backside vias. A back end of line structure is formed on a first surface of the front end of line structure. A backside structure is formed on a second surface of the front end of line structure opposite the first surface. The backside structure includes a backside metallization layer in direct contact with the one or more programmed backside vias.

公开(公告)号：US11984401B2

公开(公告)日：2024-05-14

申请号：US17304460

申请日：2021-06-22

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Junli Wang ,  Mukta Ghate Farooq ,  Dechao Guo

IPC: H01L23/00 ,  H01L21/02 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L23/5286 ,  H01L21/02532 ,  H01L21/0259 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/823871 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78696

Abstract: A semiconductor device including a hybrid contact scheme for stacked FET is disclosed with integration of a BSPDN. A double-sided (both frontside and backside of the wafer) contact scheme with buried power rail (BPR) and backside power distribution network (BSPDN) provides optimum contact and interconnect. The stacked FET could include, for example, FINFET over FINFET, FINFET over nanosheet, or nanosheet over nanosheet.