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公开(公告)号：US20230034436A1
公开(公告)日：2023-02-02
申请号：US17366640
申请日：2020-01-16
Applicant: International Business Machines Corporation
Inventor： Albert Frisch , Harry Barowski , Dominik Steenken , David Bucher , Gawel Kus , Isabel Haide , Jan Müggenburg
Abstract: A quantum circuit arrangement with at least one quantum circuit for carrying out a computation on a quantum computer, the quantum circuit arrangement comprising at least a lookup structure being configured for determining a value of a defined function based on a variable represented by a set of qubits, and a binning structure being configured to identify a defined bin based on the variable, wherein the lookup structure is adapted to determine the value of the defined function based on the bin. Further a method implementable on a classical computer for compiling a quantum circuit arrangement with at least one quantum circuit for carrying out a computation on a quantum computer.
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公开(公告)号：US10593420B2
公开(公告)日：2020-03-17
申请号：US15898861
申请日：2018-02-19
Applicant: International Business Machines Corporation
Inventor： Harry Barowski , Sheldon Levenstein , Pradip Patel , Daniel Rodko , Gordon B. Sapp , Rolf Sautter
Abstract: The present invention provides a system and method of testing CAMs and RAMs. In an exemplary embodiment, the system includes a multiple input signature register (MISR) logically coupled to digital outputs of a CAM, to digital inputs of a RAM, and to digital outputs of an ABIST controller circuit, where the MISR includes a plurality of L1 latch circuits logically coupled to a plurality of L2 latch circuits, a plurality of multiplexer circuits logically coupled to the plurality of L1 latch circuits, a plurality of exclusive or circuits (inner XOR circuits) logically coupled to the plurality of MUX circuits and to the plurality of L2 latch circuits, and at least two XOR circuits (outer XOR circuits), each of the outer XOR circuits logically coupled to one of the inner XOR circuits, to at least one of the MUX circuits, and to at least one of the L2 latch circuits.
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公开(公告)号：US10534884B2
公开(公告)日：2020-01-14
申请号：US16435890
申请日：2019-06-10
Applicant: International Business Machines Corporation
Inventor： Harry Barowski , Harald D. Folberth , Joachim Keinert , Sourav Saha
IPC: G06F17/50
Abstract: Generating a layout of an integrated circuit chip area from a description of an integrated circuit (IC). The description includes a register-transfer-level (RTL) design. The RTL design is partitioned in large blocks for synthesis of large block synthesis (LBS) blocks. The description of the IC further includes a floorplan for the IC, wherein each LBS block to be synthesized is assigned to a respective rectilinear shape in the floorplan and the rectilinear shapes do not overlap each other.
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公开(公告)号：US10417366B2
公开(公告)日：2019-09-17
申请号：US16174845
申请日：2018-10-30
Applicant: International Business Machines Corporation
Inventor： Harry Barowski , Harald D. Folberth , Joachim Keinert , Sourav Saha
IPC: G06F17/50
Abstract: Generating a layout of an integrated circuit chip area from a description of an integrated circuit (IC). The description includes a register-transfer-level (RTL) design. The RTL design is partitioned in large blocks for synthesis of large block synthesis (LBS) blocks. The description of the IC further includes a floorplan for the IC, wherein each LBS block to be synthesized is assigned to a respective rectilinear shape in the floorplan and the rectilinear shapes do not overlap each other.
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公开(公告)号：US10367481B2
公开(公告)日：2019-07-30
申请号：US15899497
申请日：2018-02-20
Applicant: International Business Machines Corporation
Inventor： Harry Barowski , Werner Juchmes , Michael B. Kugel , Wolfgang Penth
IPC: H03K3/037 , G01R31/317 , G11C11/413 , G11C7/22 , G11C29/50 , G11C29/12 , G11C29/32
Abstract: Disclosed aspects relate to a digital logic circuit. A clock generation circuitry has both a clock generation circuitry output and an inverter circuit to generate a derivative clock signal feature by inverting an array clock signal feature. A scanable storage element has both a scanable storage element output and a set of flip-flops. A memory array is connected with the scanable storage element output and the array clock signal feature. The digital logic circuit is configured to avoid a race violation.
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Patent Agency Ranking
公开(公告)号：US10079070B2
公开(公告)日：2018-09-18
申请号：US15298360
申请日：2016-10-20
Applicant: International Business Machines Corporation
Inventor： Harry Barowski , Sheldon Levenstein , Pradip Patel , Daniel Rodko , Gordon B. Sapp , Rolf Sautter
CPC classification number: G11C29/40 , G11C15/00 , G11C29/024 , G11C29/14 , G11C29/44 , G11C2029/3602
Abstract: The present invention provides a system and method of testing CAMs and RAMs. In an exemplary embodiment, the system includes a multiple input signature register (MISR) logically coupled to digital outputs of a CAM, to digital inputs of a RAM, and to digital outputs of an ABIST controller circuit, where the MISR includes a plurality of L1 latch circuits logically coupled to a plurality of L2 latch circuits, a plurality of multiplexer circuits logically coupled to the plurality of L1 latch circuits, a plurality of exclusive or circuits (inner XOR circuits) logically coupled to the plurality of MUX circuits and to the plurality of L2 latch circuits, and at least two XOR circuits (outer XOR circuits), each of the outer XOR circuits logically coupled to one of the inner XOR circuits, to at least one of the MUX circuits, and to at least one of the L2 latch circuits.
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公开(公告)号：US20180114585A1
公开(公告)日：2018-04-26
申请号：US15298360
申请日：2016-10-20
Applicant: International Business Machines Corporation
Inventor： Harry Barowski , Sheldon Levenstein , Pradip Patel , Daniel Rodko , Gordon B. Sapp , Rolf Sautter
CPC classification number: G11C29/40 , G11C15/00 , G11C29/024 , G11C29/14 , G11C29/44 , G11C2029/3602
Abstract: The present invention provides a system and method of testing CAMs and RAMs. In an exemplary embodiment, the system includes a multiple input signature register (MISR) logically coupled to digital outputs of a CAM, to digital inputs of a RAM, and to digital outputs of an ABIST controller circuit, where the MISR includes a plurality of L1 latch circuits logically coupled to a plurality of L2 latch circuits, a plurality of multiplexer circuits logically coupled to the plurality of L1 latch circuits, a plurality of exclusive or circuits (inner XOR circuits) logically coupled to the plurality of MUX circuits and to the plurality of L2 latch circuits, and at least two XOR circuits (outer XOR circuits), each of the outer XOR circuits logically coupled to one of the inner XOR circuits, to at least one of the MUX circuits, and to at least one of the L2 latch circuits.
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公开(公告)号：US20170154148A1
公开(公告)日：2017-06-01
申请号：US15431099
申请日：2017-02-13
Applicant: International Business Machines Corporation
Inventor： Harry Barowski , Joachim Keinert , Sridhar H. Rangarajan , Haoxing Ren , Sourav Saha
IPC: G06F17/50
CPC classification number: G06F17/5077
Abstract: A method for adding an electrical interconnection within a three-dimensional integrated circuit (3-D IC) is disclosed. The method may include creating, within a design file of a 3-D IC that specifies a layout for a first chip of the 3-D IC, design data corresponding to a set of through-silicon via (TSV) reservation areas. The method may also include receiving an engineering change order (ECO) and releasing, in response to the ECO, at least one TSV reservation area for reuse. The method may also include adding, by re-using at least one TSV reservation area, an electrical interconnection within the design file of the first chip of the 3-D IC.
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公开(公告)号：US09633928B2
公开(公告)日：2017-04-25
申请号：US14852335
申请日：2015-09-11
Applicant: International Business Machines Corporation
Inventor： Harry Barowski , Joachim Keinert , Sridhar H. Rangarajan , Haoxing Ren , Sourav Saha
IPC: H01L25/00 , H01L23/48 , H01L25/065 , H01L23/00 , H01L23/528
CPC classification number: H01L23/481 , H01L23/5283 , H01L24/05 , H01L24/13 , H01L24/16 , H01L25/0657 , H01L2224/0401 , H01L2224/05567 , H01L2224/13017 , H01L2224/16146 , H01L2224/16227 , H01L2225/06541 , H01L2225/06548 , H01L2924/1426 , H01L2924/1431 , H01L2924/00014
Abstract: A through-silicon via access device (TSVAD) for establishing an electrical connection to a through-silicon via (TSV) located in a planar stack of semiconductor chips is disclosed. The TSVAD may include a switching circuit, having a conductive pad terminal, a TSV terminal, an input terminal coupled to a sending logic circuit, an output terminal coupled to a receiving logic circuit, and logic devices to, in response to control signals, couple the TSV terminal to the conductive pad terminal, in one configuration, and couple the TSV terminal to another terminal in another configuration. The TSVAD may also include a control circuit to generate control signals to cause an input selection circuit to drive a signal from the sending logic circuit onto the input terminal, and to cause an output selection circuit to drive a logic signal from the output terminal to the receiving logic circuit.
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公开(公告)号：US20170004239A1
公开(公告)日：2017-01-05
申请号：US14788819
申请日：2015-07-01
Applicant: International Business Machines Corporation
Inventor： Harry Barowski , Joachim Keinert , Sourav Saha , Thomas Strach
IPC: G06F17/50
CPC classification number: G06F17/5081 , G06F17/5072 , G06F17/5077 , G06F2217/82 , G06F2217/84
Abstract: A method, executed by one or more processors, includes receiving IR-drop information as a function of location for a placement for a plurality of circuit blocks corresponding to an integrated circuit, calculating a target density for decoupling capacitors as a function of location based on the IR-drop information, placing a plurality of decoupling capacitors according to the target density to provide placed decoupling capacitors. The placed decoupling capacitors may be locally clustered to improve decoupling performance. The method may also include incrementally moving circuit elements or placed decoupling capacitors to avoid collisions within one or more circuit blocks, and routing the integrated circuit. A corresponding computer program product and computer system are also disclosed herein.
Abstract translation: 一种由一个或多个处理器执行的方法包括：接收作为与集成电路相对应的多个电路块的放置位置的函数的IR投影信息，根据位置计算用于去耦电容器的目标密度，作为位置的函数 IR-drop信息，根据目标密度放置多个去耦电容器以提供放置的去耦电容器。 放置的去耦电容器可以局部聚集以改善去耦性能。 该方法还可以包括递增移动的电路元件或放置的去耦电容器以避免一个或多个电路块内的冲突，以及布线集成电路。 本文还公开了相应的计算机程序产品和计算机系统。
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