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公开(公告)号：US11869783B2
公开(公告)日：2024-01-09
申请号：US17244084
申请日：2021-04-29
Applicant: International Business Machines Corporation
Inventor： Benjamin D. Briggs , Lawrence A. Clevenger , Nicholas A. Lanzillo , Michael Rizzolo , Theodorus E. Standaert , James Stathis
CPC classification number: H01L21/67271 , G06N5/04 , G06N20/00
Abstract: One or more processors determine a predicted sorting bin of a semiconductor device, based on measurement and test data performed on the semiconductor device subsequent to a current metallization layer. A current predicted sorting bin and a target sorting bin are determined by a machine learning model for the semiconductor device; the target bin include higher performance semiconductor devices than the predicted sorting bin. The model determines a performance level improvement attainable by adjustments made to process parameters of subsequent metallization layers of the semiconductor device. Adjustments to process parameters are generated, based on measurement and test data of the current metallization layer of semiconductor device, and the adjustment outputs for the process parameters of the subsequent metallization layers of the semiconductor device are made available to the one or more subsequent metallization layer processes by a feed-forward mechanism.
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公开(公告)号：US11105856B2
公开(公告)日：2021-08-31
申请号：US16189295
申请日：2018-11-13
Applicant: International Business Machines Corporation
Inventor： Emily A. Ray , Emmanuel Yashchin , Peilin Song , Kevin G. Stawiasz , Barry Linder , Alan Weger , Keith A. Jenkins , Raphael P. Robertazzi , Franco Stellari , James Stathis
IPC: G06F11/22 , G01R31/3193 , G01R31/319
Abstract: Methods and systems of detecting chip degradation are described. A processor may execute a test on a device at a first time, where the test includes executable instructions for the device to execute a task under specific conditions relating to a performance attribute. The processor may receive performance data indicating a set of outcomes from the task executed by the device during the test. The processor may determine a first value of a parameter of the performance attribute based on the identified subset. The processor may compare the first value with a second value of the parameter of the performance attribute. The second value is based on an execution of the test on the device at a second time. The processor may determine a degradation status of the device based on the comparison of the first value with the second value.
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公开(公告)号：US20190122911A1
公开(公告)日：2019-04-25
申请号：US15791451
申请日：2017-10-24
Applicant: International Business Machines Corporation
Inventor： Benjamin D. Briggs , Lawrence A. Clevenger , Nicholas A. Lanzillo , Michael Rizzolo , Theodorus E. Standaert , James Stathis
Abstract: One or more processors determine a predicted sorting bin of a semiconductor device, based on measurement and test data performed on the semiconductor device subsequent to a current metallization layer. A current predicted sorting bin and a target soring bin are determined by a machine learning model for the semiconductor device; the target bin include higher performance semiconductor devices than the predicted sorting bin. The model determines a performance level improvement attainable by adjustments made to process parameters of subsequent metallization layers of the semiconductor device. Adjustments to process parameters are generated, based on measurement and test data of the current metallization layer of semiconductor device, and the adjustment outputs for the process parameters of the subsequent metallization layers of the semiconductor device are made available to the one or more subsequent metallization layer processes by a feed-forward mechanism.
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公开(公告)号：US10830841B1
公开(公告)日：2020-11-10
申请号：US16445690
申请日：2019-06-19
Applicant: International Business Machines Corporation
Inventor： Nicholas Anthony Lanzillo , Benjamin D. Briggs , Michael Rizzolo , Lawrence A. Clevenger , Theodorus E. Standaert , James Stathis
Abstract: A semiconductor device includes a device magnetic tunnel junction (MTJ) and sensor MTJs. A spin polarization of a free layer of the device MTJ is configurable based at least in part on electrical energy supplied to the device MTJ. A spin polarization of a corresponding free layer of each sensor MTJ is configurable based at least in part on a magnetic field created by the spin polarization of the free layer of the device MTJ. A circuit disposed is in electrical communication with the plurality of sensor MTJs and configured to determine the corresponding free layer spin polarizations of each of the sensor MTJs based at least in part on electrical energy supplied to the sensor MTJs by the circuit. The circuit is configured to determine a magnetoresistance of the device MTJ based at least in part on the determined corresponding free layer spin polarizations of the sensor MTJ.
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Patent Agency Ranking
公开(公告)号：US20200150181A1
公开(公告)日：2020-05-14
申请号：US16189295
申请日：2018-11-13
Applicant: International Business Machines Corporation
Inventor： Emily A. Ray , Emmanuel Yashchin , Peilin Song , Kevin G. Stawiasz , Barry Linder , Alan Weger , Keith A. Jenkins , Raphael P. Robertazzi , Franco Stellari , James Stathis
IPC: G01R31/3193 , G01R31/319
Abstract: Methods and systems of detecting chip degradation are described. A processor may execute a test on a device at a first time, where the test includes executable instructions for the device to execute a task under specific conditions relating to a performance attribute. The processor may receive performance data indicating a set of outcomes from the task executed by the device during the test. The processor may determine a first value of a parameter of the performance attribute based on the identified subset. The processor may compare the first value with a second value of the parameter of the performance attribute. The second value is based on an execution of the test on the device at a second time. The processor may determine a degradation status of the device based on the comparison of the first value with the second value.
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公开(公告)号：US20210249288A1
公开(公告)日：2021-08-12
申请号：US17244084
申请日：2021-04-29
Applicant: International Business Machines Corporation
Inventor： Benjamin D. Briggs , Lawrence A. Clevenger , Nicholas A. Lanzillo , Michael Rizzolo , Theodorus E. Standaert , James Stathis
Abstract: One or more processors determine a predicted sorting bin of a semiconductor device, based on measurement and test data performed on the semiconductor device subsequent to a current metallization layer. A current predicted sorting bin and a target sorting bin are determined by a machine learning model for the semiconductor device; the target bin include higher performance semiconductor devices than the predicted sorting bin. The model determines a performance level improvement attainable by adjustments made to process parameters of subsequent metallization layers of the semiconductor device. Adjustments to process parameters are generated, based on measurement and test data of the current metallization layer of semiconductor device, and the adjustment outputs for the process parameters of the subsequent metallization layers of the semiconductor device are made available to the one or more subsequent metallization layer processes by a feed-forward mechanism.
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公开(公告)号：US11049744B2
公开(公告)日：2021-06-29
申请号：US15791451
申请日：2017-10-24
Applicant: International Business Machines Corporation
Inventor： Benjamin D. Briggs , Lawrence A. Clevenger , Nicholas A. Lanzillo , Michael Rizzolo , Theodorus E. Standaert , James Stathis
Abstract: One or more processors determine a predicted sorting bin of a semiconductor device, based on measurement and test data performed on the semiconductor device subsequent to a current metallization layer. A current predicted sorting bin and a target soring bin are determined by a machine learning model for the semiconductor device; the target bin include higher performance semiconductor devices than the predicted sorting bin. The model determines a performance level improvement attainable by adjustments made to process parameters of subsequent metallization layers of the semiconductor device. Adjustments to process parameters are generated, based on measurement and test data of the current metallization layer of semiconductor device, and the adjustment outputs for the process parameters of the subsequent metallization layers of the semiconductor device are made available to the one or more subsequent metallization layer processes by a feed-forward mechanism.
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公开(公告)号：US10796833B2
公开(公告)日：2020-10-06
申请号：US16141195
申请日：2018-09-25
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Nicholas A. Lanzillo , Benjamin D. Briggs , Michael Rizzolo , Theodorus E. Standaert , Lawrence A. Clevenger , James Stathis
Abstract: An electrical device structure including a magnetic tunnel junction structure having a first tunnel junction dielectric layer positioned between a free magnetization layer and a fixed magnetization layer. A magnetization enhancement stack present on the magnetic tunnel junction structure. The magnetization enhancement stack includes a second tunnel junction layer that is in contact with the free magnetization layer of the magnetic tunnel junction structure, a metal contact layer present on the second tunnel junction layer, and a metal electrode layer present on the metal contact layer. A metallic ring on a sidewall of the magnetic enhancement stack, wherein a base of the metallic ring may be in contact with the free magnetization layer of the magnetic tunnel junction structure.
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公开(公告)号：US20200098499A1
公开(公告)日：2020-03-26
申请号：US16141195
申请日：2018-09-25
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Nicholas A. Lanzillo , Benjamin D. Briggs , Michael Rizzolo , Theodorus E. Standaert , Lawrence A. Clevenger , James Stathis
Abstract: An electrical device structure including a magnetic tunnel junction structure having a first tunnel junction dielectric layer positioned between a free magnetization layer and a fixed magnetization layer. A magnetization enhancement stack present on the magnetic tunnel junction structure. The magnetization enhancement stack includes a second tunnel junction layer that is in contact with the free magnetization layer of the magnetic tunnel junction structure, a metal contact layer present on the second tunnel junction layer, and a metal electrode layer present on the metal contact layer. A metallic ring on a sidewall of the magnetic enhancement stack, wherein a base of the metallic ring may be in contact with the free magnetization layer of the magnetic tunnel junction structure.
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