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公开(公告)号：US10770511B2
公开(公告)日：2020-09-08
申请号：US16264935
申请日：2019-02-01
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Abstract: A magnetic random access memory (MRAM) device includes a conductor disposed in an insulating material of a lower wiring layer, a magnetic tunnel junction (MTJ) structure formed in an upper wiring layer, and a landing pad formed in an intermediary wiring layer between the lower and upper wiring layers, the landing pad extending from a top surface of the conductor to a height above the intermediary wiring layer, wherein the landing pad connects the MJT structure to the conductor.
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公开(公告)号：US10211155B2
公开(公告)日：2019-02-19
申请号：US15811129
申请日：2017-11-13
Applicant: International Business Machines Corporation
Inventor： Benjamin D. Briggs , Lawrence A. Clevenger , Nicholas A. Lanzillo , Michael Rizzolo , Theodorus E. Standaert
IPC: H01L21/4763 , H01L23/528 , H01L21/768 , H01L21/02 , H01L23/532 , H01L23/522
Abstract: Methods are provided for fabricating metallic interconnect structures having reduced electrical resistivity that is obtained by applying mechanical strain to the metallic interconnect structures, as well as semiconductor structures having metallic interconnect structures formed with permanent mechanical strain to provide reduced electrical resistivity. For example, a method includes forming a metallic interconnect structure in an interlevel dielectric (ILD) layer of a back-end-of-line (BEOL) structure of a semiconductor structure, and forming a stress layer in contact with the metallic interconnect structure. A thermal anneal process is performed to cause the stress layer to expand and apply compressive strain to the metallic interconnect structure and permanently deform at least a portion of the metallic interconnect structure into a stress memorized state of compressive strain.
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公开(公告)号：US20180328979A1
公开(公告)日：2018-11-15
申请号：US15803969
申请日：2017-11-06
Applicant: International Business Machines Corporation
Inventor： Benjamin D. Briggs , Lawrence A. Clevenger , Nicholas A. Lanzillo , Michael Rizzolo , Theodorus E. Standaert , James H. Stathis
Abstract: Embodiments of the invention are directed to a semiconductor wafer test system. A non-limiting example of the test system includes a controller, a sensing system communicatively coupled to the controller, and a stress source communicatively coupled to the controller. The controller is configured to control the stress source to deliver an applied stress to a targeted stress area of a semiconductor wafer. The sensing system is configured to detect the applied stress and provide data of the applied stress to the controller. The controller is further configured to control the stress source based at least in part on the data of the applied stress.
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公开(公告)号：US09941211B1
公开(公告)日：2018-04-10
申请号：US15468972
申请日：2017-03-24
Applicant: International Business Machines Corporation
Inventor： Benjamin D. Briggs , Lawrence A. Clevenger , Nicholas A. Lanzillo , Michael Rizzolo , Theodorus E. Standaert
IPC: H01L23/52 , H01L23/528 , H01L21/768 , H01L21/02 , H01L23/532 , H01L23/522
CPC classification number: H01L23/5329 , H01L21/02167 , H01L21/76816 , H01L21/76828 , H01L21/76846 , H01L21/76849 , H01L21/76864 , H01L23/5222 , H01L23/53238 , H01L23/53295
Abstract: Methods are provided for fabricating metallic interconnect structures having reduced electrical resistivity that is obtained by applying mechanical strain to the metallic interconnect structures, as well as semiconductor structures having metallic interconnect structures formed with permanent mechanical strain to provide reduced electrical resistivity. For example, a method includes forming a metallic interconnect structure in an interlevel dielectric (ILD) layer of a back-end-of-line (BEOL) structure of a semiconductor structure, and forming a stress layer in contact with the metallic interconnect structure. A thermal anneal process is performed to cause the stress layer to expand and apply compressive strain to the metallic interconnect structure and permanently deform at least a portion of the metallic interconnect structure into a stress memorized state of compressive strain.
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公开(公告)号：US11348872B2
公开(公告)日：2022-05-31
申请号：US16690925
申请日：2019-11-21
Applicant: International Business Machines Corporation
Inventor： Benjamin D. Briggs , Lawrence A. Clevenger , Nicholas A. Lanzillo , Takeshi Nogami , Christopher J. Penny , Michael Rizzolo
IPC: H01L23/532 , H01L23/522 , H01L21/768
Abstract: A semiconductor device is provided and includes first and second dielectrics, first and second conductive elements, a self-formed-barrier (SFB) and a liner. The first and second dielectrics are disposed with one of first-over-second dielectric layering and second-over-first dielectric layering. The first and second conductive elements are respectively suspended at least partially within a lower one of the first and second dielectrics and at least partially within the other one of the first and second dielectrics. The self-formed-barrier (SFB) is formed about a portion of one of the first and second conductive elements which is suspended in the second dielectric. The liner is deposited about a portion of the other one of the first and second conductive elements which is partially suspended in the first dielectric.
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Patent Agency Ranking
公开(公告)号：US11223655B2
公开(公告)日：2022-01-11
申请号：US16101740
申请日：2018-08-13
Applicant: International Business Machines Corporation
Inventor： Prasad Bhosale , Nicholas A. Lanzillo , Michael Rizzolo , Chih-Chao Yang
Abstract: An example operation may include one or more of identifying a current tool configuration used by a tool device to construct semiconductor devices, retrieving a smart contract stored in a blockchain to identify whether an updated tool configuration exists, responsive to identifying the updated tool configuration, transmitting an update that includes the updated tool configuration to the tool device, and responsive to receiving the updated tool configuration at the tool device, initiating construction of the semiconductor devices.
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公开(公告)号：US20190165042A1
公开(公告)日：2019-05-30
申请号：US16264935
申请日：2019-02-01
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
CPC classification number: H01L27/228 , G11C11/161 , H01L43/02 , H01L43/08 , H01L43/12
Abstract: A magnetic random access memory (MRAM) device includes a conductor disposed in an insulating material of a lower wiring layer, a magnetic tunnel junction (MTJ) structure formed in an upper wiring layer, and a landing pad formed in an intermediary wiring layer between the lower and upper wiring layers, the landing pad extending from a top surface of the conductor to a height above the intermediary wiring layer, wherein the landing pad connects the MJT structure to the conductor.
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公开(公告)号：US20190013278A1
公开(公告)日：2019-01-10
申请号：US16131553
申请日：2018-09-14
Applicant: International Business Machines Corporation
Inventor： Benjamin D. Briggs , Lawrence A. Clevenger , Nicholas A. Lanzillo , Takeshi Nogami , Christopher J. Penny , Michael Rizzolo
IPC: H01L23/532 , H01L21/768 , H01L23/522
Abstract: A semiconductor device is provided and includes first and second dielectrics, first and second conductive elements, a self-formed-barrier (SFB) and a liner. The first and second dielectrics are disposed with one of first-over-second dielectric layering and second-over-first dielectric layering. The first and second conductive elements are respectively suspended at least partially within a lower one of the first and second dielectrics and at least partially within the other one of the first and second dielectrics. The self-formed-barrier (SFB) is formed about a portion of one of the first and second conductive elements which is suspended in the second dielectric. The liner is deposited about a portion of the other one of the first and second conductive elements which is partially suspended in the first dielectric.
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公开(公告)号：US20180277482A1
公开(公告)日：2018-09-27
申请号：US15811129
申请日：2017-11-13
Applicant: International Business Machines Corporation
Inventor： Benjamin D. Briggs , Lawrence A. Clevenger , Nicholas A. Lanzillo , Michael Rizzolo , Theodorus E. Standaert
IPC: H01L23/528 , H01L23/532 , H01L23/522 , H01L21/768 , H01L21/02
CPC classification number: H01L23/5283 , H01L21/02167 , H01L21/76816 , H01L21/76828 , H01L21/76846 , H01L21/76849 , H01L21/76864 , H01L23/5222 , H01L23/5226 , H01L23/53223 , H01L23/53238 , H01L23/5329 , H01L23/53295
Abstract: Methods are provided for fabricating metallic interconnect structures having reduced electrical resistivity that is obtained by applying mechanical strain to the metallic interconnect structures, as well as semiconductor structures having metallic interconnect structures formed with permanent mechanical strain to provide reduced electrical resistivity. For example, a method includes forming a metallic interconnect structure in an interlevel dielectric (ILD) layer of a back-end-of-line (BEOL) structure of a semiconductor structure, and forming a stress layer in contact with the metallic interconnect structure. A thermal anneal process is performed to cause the stress layer to expand and apply compressive strain to the metallic interconnect structure and permanently deform at least a portion of the metallic interconnect structure into a stress memorized state of compressive strain.
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公开(公告)号：US10746782B2
公开(公告)日：2020-08-18
申请号：US15803969
申请日：2017-11-06
Applicant: International Business Machines Corporation
Inventor： Benjamin D. Briggs , Lawrence A. Clevenger , Nicholas A. Lanzillo , Michael Rizzolo , Theodorus E. Standaert , James H. Stathis
Abstract: Embodiments of the invention are directed to a semiconductor wafer test system. A non-limiting example of the test system includes a controller, a sensing system communicatively coupled to the controller, and a stress source communicatively coupled to the controller. The controller is configured to control the stress source to deliver an applied stress to a targeted stress area of a semiconductor wafer. The sensing system is configured to detect the applied stress and provide data of the applied stress to the controller. The controller is further configured to control the stress source based at least in part on the data of the applied stress.
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