公开(公告)号：US20140215429A1

公开(公告)日：2014-07-31

申请号：US13749925

申请日：2013-01-25

Applicant: International Business Machines Corporation

Inventor： Jeanne P. Bickford ,  Eric A. Foreman ,  Mark W. Kuemerle ,  Susan K. Lichtensteiger

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F2217/02

Abstract: Methods determine temperature and voltage relationships for integrated circuit library elements to produce a continuous temperature-voltage function. Some of the library elements can be used or combined to form an integrated circuit design. Further, the performance characteristics for integrated circuit chips produced according to the integrated circuit design can be defined, such performance characteristics include an operating temperature range, etc. The continuous temperature-voltage function is applied to the performance characteristics to determine a plurality of temperature/voltage combinations for the integrated circuit chips. Each of the temperature/voltage combinations comprises an operating voltage for each operating temperature within the operating temperature range of the integrated circuit chips. Next, the integrated circuit chips are produced according to the integrated circuit design. The temperature/voltage combinations are recorded in memory of the integrated circuit chips.

Abstract translation: 方法确定集成电路库元件的温度和电压关系，以产生连续的温度 - 电压功能。 一些库元素可以被使用或组合以形成集成电路设计。 此外，可以定义根据集成电路设计制造的集成电路芯片的性能特性，这种性能特征包括工作温度范围等。连续温度 - 电压功能被应用于性能特性以确定多个温度/ 集成电路芯片的电压组合。 每个温度/电压组合包括在集成电路芯片的工作温度范围内的每个工作温度的工作电压。 接下来，根据集成电路设计制造集成电路芯片。 温度/电压组合记录在集成电路芯片的存储器中。

公开(公告)号：US20150028937A1

公开(公告)日：2015-01-29

申请号：US13948912

申请日：2013-07-23

Applicant: International Business Machines Corporation

Inventor： Jean P.S. Bickford ,  Eric A. Foreman ,  David J. Hathaway ,  Mark W. Kuemerle ,  Susan K. Lichtensteiger

IPC: G05F1/46 ,  H03L7/00

CPC classification number: G05F1/463 ,  H03L1/02

Abstract: Various embodiments include approaches for controlling a supply voltage or a clock frequency to an integrated circuit (IC). Various additional embodiments include circuitry for controlling a supply voltage or a clock frequency of an IC. In some cases, a method includes: locating a set of temperature sensors on bin locations in an IC; determining temperature bounds of the bin locations in the IC as a function of a determined temperature at the set of temperature sensors; determining timing constraints as a function of supply voltages at the bin locations and the determined temperature at the set of temperature sensors; and determining operational voltage bounds for the IC as a function of the determined temperature at the set of temperature sensors.

Abstract translation: 各种实施例包括用于控制集成电路（IC）的电源电压或时钟频率的方法。 各种附加实施例包括用于控制IC的电源电压或时钟频率的电路。 在一些情况下，一种方法包括：在IC中的仓位置上定位一组温度传感器; 确定IC中的仓位置的温度范围作为温度传感器组上确定的温度的函数; 确定作为所述仓位置处的供应电压的函数的时间约束和所述一组温度传感器处的确定的温度; 以及根据所述一组温度传感器上确定的温度确定所述IC的工作电压范围。

公开(公告)号：US08843874B2

公开(公告)日：2014-09-23

申请号：US13929893

申请日：2013-06-28

Applicant: International Business Machines Corporation

Inventor： Jeanne P. Bickford ,  Eric A. Foreman ,  Mark W. Kuemerle ,  Susan K. Lichtensteiger

IPC: G06F17/50 ,  G01R31/30 ,  G01R31/317

CPC classification number: G06F17/5045 ,  G01R31/3004 ,  G01R31/3016 ,  G01R31/31725 ,  G06F17/5031

Abstract: A method of optimizing power and timing for an integrated circuit (IC) chip, which uses an IC technology that exhibits temperature inversion, by modifying a voltage supplied to the IC chip, while meeting power consumption and timing delay performances across lower and higher temperature ranges. A high voltage is selected that meets a closed timing analysis across a full temperature range to meet a timing performance and a low voltage is selected to meet the timing performance and the power performance across a lower temperature range to a temperature cut point in the higher temperature range. The IC chip is turned on at the high voltage and the high voltage is lowered to the low voltage when the temperature cut point is exceeded to meet the power performance while maintaining the timing performance.

Abstract translation: 一种通过修改提供给IC芯片的电压同时满足较低和较高温度范围内的功率消耗和定时延迟性能来优化集成电路（IC）芯片的功率和定时的方法，该集成电路（IC）芯片使用显示温度反转的IC技术 。 选择高电压，以满足整个温度范围内的闭合时序分析，以满足定时性能，并选择低电压以满足更高温度下的温度下降温度范围内的定时性能和功率性能 范围。 IC芯片在高电压下导通，并且当超过温度切断点时将高电压降低到低电压以满足功率性能同时保持定时性能。

公开(公告)号：US08839165B2

公开(公告)日：2014-09-16

申请号：US13749925

申请日：2013-01-25

Applicant: International Business Machines Corporation

Inventor： Jeanne P. Bickford ,  Eric A. Foreman ,  Mark W. Kuemerle ,  Susan K. Lichtensteiger

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F2217/02

Abstract: Methods determine temperature and voltage relationships for integrated circuit library elements to produce a continuous temperature-voltage function. Some of the library elements can be used or combined to form an integrated circuit design. Further, the performance characteristics for integrated circuit chips produced according to the integrated circuit design can be defined, such performance characteristics include an operating temperature range, etc. The continuous temperature-voltage function is applied to the performance characteristics to determine a plurality of temperature/voltage combinations for the integrated circuit chips. Each of the temperature/voltage combinations comprises an operating voltage for each operating temperature within the operating temperature range of the integrated circuit chips. Next, the integrated circuit chips are produced according to the integrated circuit design. The temperature/voltage combinations are recorded in memory of the integrated circuit chips.

Abstract translation: 方法确定集成电路库元件的温度和电压关系，以产生连续的温度 - 电压功能。 一些库元素可以被使用或组合以形成集成电路设计。 此外，可以定义根据集成电路设计制造的集成电路芯片的性能特性，这种性能特征包括工作温度范围等。连续温度 - 电压功能被应用于性能特性以确定多个温度/ 集成电路芯片的电压组合。 每个温度/电压组合包括在集成电路芯片的工作温度范围内的每个工作温度的工作电压。 接下来，根据集成电路设计制造集成电路芯片。 温度/电压组合记录在集成电路芯片的存储器中。

公开(公告)号：US09269407B1

公开(公告)日：2016-02-23

申请号：US14614470

申请日：2015-02-05

Applicant: International Business Machines Corporation

Inventor： Jeanne P. Bickford ,  Eric A. Foreman ,  Mark W. Kuemerle ,  Susan K. Lichtensteiger

IPC: G11C5/14

CPC classification number: G11C5/147

Abstract: Disclosed is a system that periodically increases the supply voltage applied to a power rail of an integrated circuit chip that is incorporated into a product, thereby compensating for age-dependent changes in a performance parameter sensitivity (e.g., in a delay sensitivity). In this system, the chip comprises at least a memory, an age monitor, a voltage selector and a power rail. The memory stores an age/voltage table. The age monitor automatically measures the age of the chip. Based on the age and using the age/voltage table, the voltage selector selects a specific supply voltage and outputs a voltage selection signal to an adjustable voltage regulator, which can apply (e.g., automatically or on-demand) that specific supply voltage to the power rail. Also disclosed is a method for regulating the power supplied to an integrated circuit chip, which is incorporated into a product, and a method for generating an age/voltage table.

Abstract translation: 公开了一种系统，其周期性地增加施加到整合到产品中的集成电路芯片的电源轨的电源电压，由此补偿性能参数灵敏度（例如，延迟灵敏度）中与年龄有关的变化。 在该系统中，芯片至少包括存储器，老化监视器，电压选择器和电源轨。 存储器存储年龄/电压表。 年龄监测器自动测量芯片的寿命。 根据年龄和使用年龄/电压表，电压选择器选择一个特定的电源电压，并将一个电压选择信号输出到一个可调节的电压调节器，该稳压器可以适用（例如，自动或点播）该特定的电源电压 电力轨道 还公开了一种用于调节提供给集成电路芯片的功率的方法，其被并入产品中，以及用于产生年龄/电压表的方法。

公开(公告)号：US09171125B2

公开(公告)日：2015-10-27

申请号：US14190723

申请日：2014-02-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Igor Arsovski ,  Jeanne P. Bickford ,  Mark W. Kuemerle

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5031 ,  G06F2217/78 ,  G06F2217/84

Abstract: Methods and systems are provided for that are designed to impose an n-type to p-type device skew constraint that is beyond what normal technology limits allow in order to operate semiconductor devices at lower voltages while still achieving a similar performance at a lower power. More specifically, a method is provided for that includes setting device skew requirements for at least one library element, setting device skew test dispositions for the at least one library element based on the set device skew requirements, designing the at least one library element using device skew assumptions, fabricating the at least one library element on a product that includes at least one device skew monitor, determining an actual device skew of the fabricated at least one library element using the at least one device skew monitor, and determining whether the fabricated product meets target specifications.

Abstract translation: 提供的方法和系统被设计为施加n型到p型装置偏斜约束，该约束超出正常技术限制允许以在较低电压下操作半导体器件，同时仍然在较低功率下实现类似的性能。 更具体地，提供了一种方法，其包括：针对至少一个库元素设置设备偏斜要求，基于设置的设备偏差要求来设置用于至少一个库元素的设备偏斜测试配置，使用设备来设计至少一个库元素 在产品上制造包括至少一个设备偏斜监视器的至少一个库元件，使用至少一个设备偏斜监视器确定所制造的至少一个库元件的实际设备偏差，以及确定所制造的产品 达到目标规格。

公开(公告)号：US20150046739A1

公开(公告)日：2015-02-12

申请号：US13963438

申请日：2013-08-09

Applicant: International Business Machines Corporation

Inventor： Mark W. Kuemerle ,  Paul S. Zuchowski

IPC: G06F1/26

CPC classification number: G06F1/26 ,  G06F1/3243 ,  G06F1/3296 ,  Y02D10/152 ,  Y02D10/172

Abstract: Various embodiments provide systems, computer program products and computer implemented methods. In some embodiments, the system includes a computer-implemented method of binning at least one integrated circuit chip, the method including determining a baseline operational voltage for the at least one integrated circuit chip, determining a total operational power threshold for the at least one integrated circuit chip, determining an initial performance characteristic for a first component of the at least one integrated circuit chip, operating the first component at a driving voltage higher than the baseline voltage to raise the initial performance characteristic of the first component to a raised performance characteristic while ensuring that operational power does not exceed the operational power threshold and assigning the at least one integrated circuit chip to a performance bin based on the raised performance characteristic.

Abstract translation: 各种实施例提供系统，计算机程序产品和计算机实现的方法。 在一些实施例中，该系统包括计算机实现的将至少一个集成电路芯片合并的方法，所述方法包括确定所述至少一个集成电路芯片的基准工作电压，确定所述至少一个集成电路芯片的总工作功率阈值 确定所述至少一个集成电路芯片的第一部件的初始性能特性，以高于所述基准电压的驱动电压操作所述第一部件，以将所述第一部件的初始性能特性提高到升高的性能特性，同时 确保操作功率不超过操作功率阈值，并且基于提高的性能特性将至少一个集成电路芯片分配给性能仓。

公开(公告)号：US20130326460A1

公开(公告)日：2013-12-05

申请号：US13929893

申请日：2013-06-28

Applicant: International Business Machines Corporation

Inventor： Jeanne P. Bickford ,  Eric A. Foreman ,  Mark W. Kuemerle ,  Susan K. Lichtensteiger

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G01R31/3004 ,  G01R31/3016 ,  G01R31/31725 ,  G06F17/5031

Abstract: A method of optimizing power and timing for an integrated circuit (IC) chip, which uses an IC technology that exhibits temperature inversion, by modifying a voltage supplied to the IC chip, while meeting power consumption and timing delay performances across lower and higher temperature ranges. A high voltage is selected that meets a closed timing analysis across a full temperature range to meet a timing performance and a low voltage is selected to meet the timing performance and the power performance across a lower temperature range to a temperature cut point in the higher temperature range. The IC chip is turned on at the high voltage and the high voltage is lowered to the low voltage when the temperature cut point is exceeded to meet the power performance while maintaining the timing performance.

Abstract translation: 一种通过修改提供给IC芯片的电压同时满足较低和较高温度范围内的功率消耗和定时延迟性能来优化集成电路（IC）芯片的功率和定时的方法，该集成电路（IC）芯片使用显示温度反转的IC技术 。 选择高电压，满足整个温度范围内的闭合时序分析，以满足定时性能，并选择低电压以满足更高温度范围内的较低温度范围的时序性能和功率性能 范围。 IC芯片在高电压下导通，并且当超过温度切断点时将高电压降低到低电压以满足功率性能同时保持定时性能。

公开(公告)号：US09501607B1

公开(公告)日：2016-11-22

申请号：US14734411

申请日：2015-06-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Igor Arsovski ,  Mark W. Kuemerle ,  Qing Li

IPC: G06F17/50 ,  G06F15/04

CPC classification number: G06F17/5081 ,  G06F17/5027 ,  G06F17/5031 ,  G06F17/5045 ,  G06F17/5077 ,  G06F2217/06 ,  G06F2217/66 ,  G06F2217/84

Abstract: A computing device for a generating composite view for an intellectual property (IP) core may obtain constraints for multiple application specific integrated circuits (ASIC) designs in which the IP core is used; and determine composite constraints for the IP core based on the constraints for the multiple ASIC designs. The composite constraints may be within all constraints for the multiple ASIC designs. A freedom of change to update the particular IP core may be identified based on the composite constraints.

Abstract translation: 用于知识产权（IP）核心的生成复合视图的计算设备可以获得其中使用IP核的多个专用集成电路（ASIC）设计的约束; 并基于多个ASIC设计的约束来确定IP核的复合约束。 复合约束可以在多个ASIC设计的所有约束内。 可以基于复合约束来识别更新特定IP核的自由。

公开(公告)号：US20150025857A1

公开(公告)日：2015-01-22

申请号：US13947155

申请日：2013-07-22

Applicant: International Business Machines Corporation

Inventor： Igor Arsovski ,  Robert M. Houle ,  Mark W. Kuemerle

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5022 ,  G06F2217/10 ,  G06F2217/78

Abstract: A method for predicting the power consumption of a semiconductor chip is provided. A plurality of statistical distributions characterizing a plurality of power contributing parameters for a plurality of power consuming units included in the semiconductor chip is received. A statistical distribution characterizing the power consumption is determined based on the received plurality of statistical distributions and based on the correlation between the plurality of power contributing parameters.

Abstract translation: 提供了一种用于预测半导体芯片的功耗的方法。 接收表示包括在半导体芯片中的多个功率消耗单元的多个功率贡献参数的多个统计分布。 基于接收到的多个统计分布并且基于多个功率贡献参数之间的相关性来确定表征功耗的统计分布。