公开(公告)号：US20210126764A1

公开(公告)日：2021-04-29

申请号：US16667872

申请日：2019-10-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Troy Beukema

IPC: H04L7/00

Abstract: A data equalization system includes a data clock input configured to receive a clock signal. There is an input node operative to receive a data signal of transmission symbols that change state synchronously with the clock signal. There is a first tap coupled to the input node. A second tap is configured to receive a variation of the data signal. At least one of a weight of the first tap or a weight of the second tap is modulated by a dynamic control parameter that repeats synchronously with each transmission symbol.

公开(公告)号：US10812301B1

公开(公告)日：2020-10-20

申请号：US16667875

申请日：2019-10-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Troy Beukema

IPC: H04L25/03

Abstract: A dynamic tap weight generator circuit includes a clock generator circuit having a first output and a second output. There is a current interpolator circuit coupled to a first current source and a second current source and to the first and second outputs of the clock generator circuit and operative to provide a first output and a second output providing a differential output current between a current of the first current source and a current of the second current source across a symbol transmission interval. A 2:1 current multiplexer is coupled to a first and second outputs of the current interpolator circuit. A tap weight driver is coupled to an output of the 2:1 current multiplexer and configured is to dynamically adjust a tap weight of an equalizer dynamically during each clock cycle of the clock generator.

公开(公告)号：US12081642B2

公开(公告)日：2024-09-03

申请号：US16667872

申请日：2019-10-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Troy Beukema

IPC: H04L7/00

CPC classification number: H04L7/0008 ,  H04L7/0037 ,  H04L7/0058

Abstract: A data equalization system includes a data clock input configured to receive a clock signal. There is an input node operative to receive a data signal of transmission symbols that change state synchronously with the clock signal. There is a first tap coupled to the input node. A second tap is configured to receive a variation of the data signal. At least one of a weight of the first tap or a weight of the second tap is modulated by a dynamic control parameter that repeats synchronously with each transmission symbol.

公开(公告)号：US09660660B1

公开(公告)日：2017-05-23

申请号：US15273397

申请日：2016-09-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Troy Beukema ,  Yong Liu ,  Sergey Rylov ,  Mihai A. Sanduleanu ,  Zeynep Toprak Deniz

IPC: H03M1/06 ,  H03M1/10 ,  H03M1/12 ,  H03M7/16 ,  H03M1/36

CPC classification number: H03M1/1023 ,  H03M1/069 ,  H03M1/124 ,  H03M1/1245 ,  H03M1/164 ,  H03M1/361

Abstract: An analog-to-digital converter includes a plurality of slave sampler multiplexers responsive to outputs of a master sampler that receives analog signals and whose output ports connect to integrating threshold comparators having capacitive digital-to-analog conversion offset adjustments for forming an analog-to-thermometer code conversion. A calibration state machine receives outputs of each of the integrating threshold comparators to control the capacitive digital-to-analog conversion offset adjustment of every integrating threshold comparator and to control a calibration digital-to analog converter. A thermometer code to binary code logic decoder receives outputs of each of the integrating threshold comparators and outputs digital samples.

公开(公告)号：US09571115B1

公开(公告)日：2017-02-14

申请号：US14941245

申请日：2015-11-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Troy Beukema ,  Yong Liu ,  Sergey Rylov ,  Mihai A. Sanduleanu ,  Zeynep Toprak Deniz

IPC: H03M1/06 ,  H03M1/10 ,  H03M1/12 ,  H03M1/36 ,  H03M7/16

CPC classification number: H03M1/1023 ,  H03M1/069 ,  H03M1/124 ,  H03M1/1245 ,  H03M1/164 ,  H03M1/361

Abstract: An analog-to-digital converter includes a plurality of slave sampler multiplexers responsive to outputs of a master sampler that receives analog signals and whose output ports connect to integrating threshold comparators having capacitive digital-to-analog conversion offset adjustments for forming an analog-to-thermometer code conversion. A calibration state machine receives outputs of each of the integrating threshold comparators to control the capacitive digital-to-analog conversion offset adjustment of every integrating threshold comparator and to control a calibration digital-to analog converter. A thermometer code to binary code logic decoder receives outputs of each of the integrating threshold comparators and outputs digital samples.

Abstract translation: 模数转换器包括响应于主采样器的输出的多个从取样器多路复用器，其接收模拟信号，并且其输出端口连接到具有电容性数模转换偏移调整的积分阈值比较器，以形成模拟到 - 温度计代码转换。 校准状态机接收每个积分阈值比较器的输出，以控制每个积分阈值比较器的电容性数模转换偏移调整，并控制校准数模转换器。 二进制码逻辑解码器的温度计代码接收每个积分阈值比较器的输出并输出数字样本。